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9042503 Data recovery circuit and operation method thereof  
In a data recovery circuit, a sampling circuit is configured to sample data using a plurality of sampling clock signals having different phases relative to one another and to output a plurality of...
9042404 Scalable interconnect modules with flexible channel bonding  
The present application discloses apparatus and methods for increasing channel utilization for a high-speed serial interface of an integrated circuit (IC). A new circuit architecture is disclosed...
9042431 Wide band deterministic interface  
A transceiver with non-deterministic delay characteristics is analyzed and adjusted to provide a transceiver with deterministic delay characteristics. The transceiver may be implemented with a...
9036686 System and method for initiating 3GPP modem online data states  
A modem and a method of placing a modem in an online data state. In one embodiment, the modem includes: (1) a digital interface configured to receive, via an AT channel thereof, a standard AT...
9036763 Methods and devices for implementing all-digital phase locked loop  
An all-digital phase locked loop includes a time to digital converter that determines a fractional portion of a phase count. The time to digital converter has a quantization error that may be...
9036754 Circuit for a radio system, use and method for operation  
A circuit and method of operation for a circuit of a radio system in which a system time is divided into symbols, in which a system clock generator is activated in an operating mode, so that the...
9036759 Method and apparatus for performing synchronization between devices  
A method performed by a device for performing synchronization between devices for a Device-to-Device (D2D) communication is provided. The method includes setting, according to a process of the...
9031736 Channel diagnostic system for sent receiver  
A system for performing diagnostic checks on a data message transmitted from a sensor and received by a receiver includes a receiver clock tick counter, a prescaler counter, a calibration pulse...
9031181 Method and apparatus for controlling clocking of transceivers in a multi-port networking device  
A multi-port information communication system includes a reference clock signal generator configured to generate a reference clock signal. The system also includes a phase controller configured to...
9030339 Transmitting device and receiving device  
A transmitting device includes a parallel data generation unit and a transmitting unit. The parallel data generation unit generates first serial data and second serial data from a data packet,...
9025964 Receiver, data identifying and reproducing apparatus, pon system, and data identifying and reproducing method  
An OLT that receives a signal in which transmission signals having a plurality of transmission rates are time-division multiplexed, as a received signal, and performs data reproduction by...
9025674 Method for reconstructing digital video data stream and apparatus thereof  
An apparatus for reconstructing digital video data stream reconstructs a transport stream from a first data stream and a second data stream. Both of the first data stream and the second data...
9025712 Sensor, clock frequency adjusting system and method thereof  
A clock frequency adjusting system is disclosed. The clock frequency adjusting system includes a sensing clock generating unit, a frequency-dividing unit and a controller. The frequency-dividing...
9025650 Multiple receivers in an OFDM/OFDMA communication system  
A signal receiver is configured to receive multiple time-domain input signals. A plurality of the input signals among the multiple time-domain input signals is selected and transformed into...
9020087 All digital burst-mode clock and data recovery (CDR)  
The present invention relates to a clock and data recovery (CDR) unit comprising of a bang-bang phase detector to receive data and a recovered clock from a phase selector multiplexer. The phase...
9020084 High frequency synchronizer  
Techniques for resolving a metastable state in a synchronizer are described herein. In one embodiment, a circuit for resolving a metastable state in a synchronizer comprises a signal delay circuit...
9014321 Clock drift compensation interpolator adjusting buffer read and write clocks  
In at least some embodiments, an electronic device includes a data sink and a buffer coupled to the data sink. The buffer is configured to receive streaming data in transit to the data sink. The...
9014285 Receiving apparatus and receiving method  
An object of the present invention is to provide a receiving apparatus and a receiving method capable of preventing phase rotation of a signal after FFT from occurring on a frequency domain....
9014322 Low power and compact area digital integrator for a digital phase detector  
In an example embodiment, a phase-locked loop circuit may include a first circuitry to receive a reference signal and a source signal. The first circuitry may generate a correction signal for...
9008251 Adaptive phase-shifted synchronization clock generation circuit and method for generating phase-shifted synchronization clock  
The present invention discloses an adaptive phase-shifted synchronization clock generation circuit and a method for generating phase-shifted synchronization clock. The adaptive phase-shifted...
9008252 Circuit, method and mobile communication device  
A circuit includes an oscillator, a variable phase adjuster and a feedback loop. The oscillator is configured to provide an RF signal, wherein the oscillator is configured to operate in a...
9008158 Apparatus for transmitting and receiving signal in communication system  
Disclosed uses a digital to analog converter and an analog to digital converter that process a low bit for processing of a data signal at high speed according to analog to digital conversion and...
9001275 Method and system for improving audio fidelity in an HDMI system  
HDMI is a digital audio and video communications protocol commonly used in consumer electronics. HDMI is particularly synonymous with high fidelity audio and video. Even though HDMI is a digital...
9001865 System and device for generating reference signal, and timing signal supply device  
Provided is a timing signal supply device that can frequently perform a phase comparison on a side of receiving a supply of a timing signal and flexibly achieve various operation modes. A GPS...
9001950 Information processing apparatus, serial communication system, method of initialization of communication therefor, and serial communication apparatus  
The disclosure provides a technique of enabling to confirm the state of a partner apparatus in high-speed serial communication. An information processing apparatus including a master and a slave...
8995599 Techniques for generating fractional periodic signals  
A phase-locked loop circuit includes phase detection circuitry to generate a first control signal based on a phase comparison between first and second periodic signals. An oscillator circuit...
8995595 Method and apparatus for receiving burst data without using external detection signal  
Apparatus and method for receiving burst data signal without using external detection signal are disclosed. The apparatus can include a clock data recovery (CDR) circuit to generate a clock...
8989321 Preamble detection based on repeated preamble codes  
Systems, methods, and other embodiments associated with preamble detection based on repeated preamble codes are described. According to one embodiment, an apparatus is provided that wirelessly...
8989330 Method and apparatus to detect a synchronization delimiter  
A technique includes receiving a datum indicative of a candidate delimiter in a receiver; and processing the datum in a machine to determine whether the datum indicates a synchronization...
8989328 Systems and methods for serial communication  
This disclosure includes a point-to-point two-lineserial interface (TSI) suitable for use in a wireless communications device as well as in other applications. The TSI may employ a protocol...
8989324 Receiver and receiving method  
Embodiments of the present invention provide a receiver and a receiving method. The receiver comprises: a branch forming unit a plurality of signal branches; each of the signal branches comprising...
8989652 Advanced timing and time transfer for satellite constellations using crosslink ranging and an accurate time source  
A system, method, and apparatus for advanced timing and time transfer for satellite constellations using crosslink ranging and an accurate time source are disclosed herein. In particular, the...
8989327 Method and apparatus for transmitting or detecting a primary synchronization signal  
A method and apparatus for transmitting or detecting primary synchronization signal. The receiver receives primary synchronization signal from a transmitter, and detects the sequence used in the...
8983014 Receiver circuit and semiconductor integrated circuit  
In a receiver circuit which can correct a deviation of phase between an input signal and a clock, a sampler detects an amplitude level of the input signal at timing indicated by the clock, a first...
8982935 Apparatus and method for ranging using round-trip time by broadcasting in a network  
A method, an apparatus, and a computer program product for wireless communication are provided. The apparatus receives a first message from a first wireless communication device and a second...
8982974 OFDM clock recovery  
Receiver synchronization techniques (RST), contributing more accurate synchronization of receiver clock to OFDM composite frame combined with much faster acquisition time and better stability of...
8983012 Receive timing manager  
A novel receive timing manager is presented. The preferred embodiment of the present invention comprises an edge detection logic to detect the data transition points, a plurality of data...
8976051 Floating point timer techniques  
Aspects of the present disclosure relate to floating point timers and counters that are used in a variety of contexts. In some implementations, a floating point counter can be used to generate a...
8976919 Low power communication device for scheduling data segments using hold time or lock time of phase locked loop  
A device communicating with a node, includes a communication unit configured to transmit a transmitting data segment to the node, and receive a receiving data segment from the node. The device...
8971468 Increasing the resolution of serial data recovery units (DRUs) based on interleaved free running oversamplers  
The methods and apparatus disclosed herein provide an operative system for increasing the resolution of serial DRUs based on interleaved free running oversamplers. In particular, this system uses...
8971424 Combining pilot-symbol-based phase estimation with data-symbol-based phase estimation  
A method for a receiver to estimate phase of a carrier wave, including receiving a carrier wave carrying pilot symbols and data symbols extending between the pilot symbols, determining phase of...
8971321 System and method for accelerating and decelerating packets  
In one embodiment, a system for accelerating a packet stream includes a first accelerator configured to re-clock the packet stream from a first clock rate to a second clock rate to produce an...
8971397 On-the-fly compensation of sampling frequency and phase offset in receiver performing ultra-high-speed wireless communication  
Received data oversampled twice is polyphased by the receiver, feedback is applied using an adaptive algorithm, and the filter coefficients (tap coefficient sequence) of a compensation filter are...
8971471 Predictable coding delay over communications networks  
A decoder includes a buffer configured to incrementally transport a synchronous data stream through a path of the decoder. A control circuit is configured to control a depth parameter associated...
8964918 IC first, second communication circuits each with three communication states  
Data is communicated through two separate circuits or circuit groups, each having clock and mode inputs, by sequentially reversing the role of the clock and mode inputs. The data communication...
8964924 Method and device for clock recovery  
A method and a device for processing a signal determine a timing phase over an observation interval of an input signal. A frequency estimation is determined based on the timing phase. A phase...
8964899 Receiving circuit  
Disclosed is a receiving circuit which includes: a data selection circuit selecting two input data located while placing in between the center phase of one unit interval of a binary input data; a...
8964862 Transmission method and system  
A method for transmitting digital data via a line includes the steps of providing a clock signal and of transmitting the digital data in synchrony with the clock signal, the clock signal having a...
8964919 System and method for determining a time for safely sampling a signal of a clock domain  
A system and method are provided for determining a time for safely sampling a signal of a clock domain. In one embodiment, a phase estimate of a first clock domain is calculated based on a...
8964922 Adaptive frequency synthesis for a serial data interface  
Various embodiments of the present invention relate to systems, devices and methods of oversampling electronic components where high frequency oversampling clock signals are generated internally....