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7194556 |
Method and apparatus for high accuracy distributed time synchronization using processor tick counters
A method and apparatus are provided that allow processing engines to be synchronized to each other with high accuracy. In one embodiment, the invention includes obtaining a processor tick counter...
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7194648 |
Process for time synchronization of at least two clocks in a microprocessor system
A method for time synchronisation of at least two clocks contained in a multiprocessor system, wherein a first clock having a predetermined clock rate generates consecutive respective time-stamps...
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7190736 |
Technique to simultaneously distribute clock signals and data on integrated circuits, interposers, and circuit boards
A technique is described for simultaneously and synchronously transmitting digital data and a clock signal in a digital integrated circuit, circuit board, or system. The technique is based on the...
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7190963 |
Method for performing frequency synchronization of a base station and a network part
The invention relates to a method for performing frequency synchronization of a base station, and to a network part. In the method, the following operations are performed: maintaining a reference...
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7187740 |
Communications system
A communication system is provided in which normal communications can be ensured even upon a loss of synchronization on a part of transmission paths configuring a network. The system is to perform...
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7187737 |
Data transmitting unit, data communicating apparatus and data communicating method
In a transmitting apparatus 101, there are provided PLL circuit 601 for generating high-speed clock signals up to 2 m times (m being a positive integer) from a basic clock signal, and a clock...
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7184507 |
Residual phase error correction
A phase error correction technique in data communication receivers such as WLAN (Wireless Local Area Network) receivers is provided. A signal having a phase error is received, and a phase error...
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7184503 |
Multi-loop circuit capable of providing a delayed clock in phase locked loops
A multi-loop circuit includes a first switching device to receive a first clock pulse and a second delayed pulse and produce a first output pulse including either the first clock pulse or the...
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7184484 |
Method and apparatus for serial data communication
A method and an apparatus for serial data communication employs a data transmission process which transmits data from one control unit to the another control unit and at the same time checks a...
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7184502 |
Circuit arrangement for recovering clock and data from a received signal
A circuit arrangement to recover clock and data from a received signal comprises an electronic commutator for sampling the received signal in such a way that several sampling values of a bit cell...
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7184501 |
Method of synchronous serial communication and system for synchronous serial communication
A method and system for serial communication capable of increasing the speed of the transmission of serial data are provided. A block mode is employed if transmission of serial data having a...
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7180970 |
Automatic link establishment using external synchronization
A system and method for synchronized communication of information between transmitting and receiving stations. The system has a first station and a second station, each attached to a modem, and a...
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7180971 |
Selecting between two TAP circuits with MODE/TCK and TCK/MODE signals
Data is communicated through two separate circuits or circuit groups, each having clock and mode inputs, by sequentially reversing the role of the clock and mode inputs. The data communication...
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7177381 |
Noise-resistive, burst-mode receiving apparatus and a method for recovering a clock signal and data therefrom
A noise-resistive, burst-mode receiving apparatus including a voltage control signal generator for multiplying a frequency of a system clock signal and generating a voltage control signal having a...
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7177379 |
DDR on-the-fly synchronization
Double data rate (DDR) synchronous dynamic random access memory (SDRAM) data is sampled into a synchronization circuit on both rising and falling edges of a data strobe (DQS) signal, into separate...
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7173992 |
Method for synchronization in wireless systems using receive diversity
A preferred embodiment of the invention is a method for synchronizing a mobile terminal comprising M diversity branches to a wireless network using diversity combination to acquire the code...
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7173994 |
Timing recovery circuit with multiple stages
A timing recovery circuit includes a first oscillating circuit configured to produce a first timing signal, a second oscillating circuit configured to produce a second timing signal, a first...
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7170960 |
Instantaneous clock recovery circuit
A clock recovery circuit ( 10 ) for a superconductor system that enables the phase of a system clock to be instantaneously reset without any pulse interaction. The clock recovery circuit ( 10 )...
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7170922 |
Transmission timing control device, digital roll-off filter, and mobile radio terminal for digital radio communication
In a mobile radio terminal at transmission timing control device, transmit data spread-modulated is delayed by a timing control portion with a timing of reception as a reference by a predetermined...
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7167536 |
Signal receiving circuit, semiconductor device and system
This invention provides a signal transfer technique capable of realizing stable high rate data transfer and the reduction of a layout area. A system (semiconductor device) for realizing a high rate...
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7167535 |
Circuit sharing for frequency and phase error correction
A WLAN (Wireless Local Area Network) receiver with a synchronization unit is provided, wherein the synchronization unit comprises a frequency error correction unit configured to perform a frequency...
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7164743 |
Delay locked loop
A delay locked loop of the present invention which synthesizes data and a clock inputted from outside has: voltage control delay loops having a plurality of delay circuit parts sequentially...
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7161999 |
Synchronizing data or signal transfer across clocked logic domains
A synchronization interface transfers multi-bit digital data or signal between multiple clocked logic domains while maintaining data or signal integrity. When deployed in a processor-based system,...
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7161998 |
Digital phase locked loop for regenerating the clock of an embedded signal
The present invention relates to a system and method for generating a first clock frequency for a plurality of digital data bursts compressed in time, where each of the plurality of digital data...
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7158593 |
Combining a clock signal and a data signal
A method of transmitting data in a system including at least one data channel and a separate clock channel is disclosed. The method involves combining a clock signal to be transmitted on the clock...
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7158594 |
Receivers for controlled frequency signals
In some embodiments, a receiver includes a first conductor to carry a magnitude encoded controlled frequency signal (CFS) and a second conductor to carry a complementary magnitude encoded...
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7158592 |
Method and apparatus for synchronizing data transfer
The invention is a method and apparatus for ensuring synchronization for digital communication between a transmitting and a receiving device, particularly when the clock and/or frame...
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7154973 |
Spreading code synchronization method, receiver, and mobile station
The present invention relates to a spreading code synchronization method and others for implementing fast cell search during entry of a mobile station into a soft handover mode in an intercell...
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7151812 |
Sample clock extracting circuit and baseband signal receiving circuit
A sample clock extracting circuit comprises including a number-of-change point memory, a number-of-change point updating circuit and an output clock phase determining circuit. The number-of-change...
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7149269 |
Receiver for clock and data recovery and method for calibrating sampling phases in a receiver for clock and data recovery
A receiver for clock and data recovery includes n sampling latches (SL 1 . . . SLn) for determining n sample values (SV 1 . . . SVn) of a reference signal (Ref 2 ) at n sampling phases (φ 1 a ....
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7149265 |
Timing recovery loop with non-integer length
A timing signal is regenerated from an encoded digital signal having a data clock frequency R b in a receiver using a predetermined sample rate F s , wherein the data clock period 1/R b is not an...
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7142129 |
Method and system for downhole clock synchronization
A method and system for use in synchronizing at least two clocks in a downhole network are disclosed. The method comprises determining a total signal latency between a controlling processing...
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7142621 |
Method and circuit for recovering a data signal from a stream of binary data
There is disclosed a data recovery (DR) circuit including an over sampling (OS) circuit, a transition detection (TD) circuit and a sample selection/data alignment (SSDA) circuit. A multiphase clock...
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7139345 |
Method and circuit for adjusting the timing of output data based on the current and future states of the output data
A clock synchronization circuit receives an input clock signal along with current and future data signals. The clock synchronization circuit generates a phase shifted clock signal in response to...
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7139344 |
Method and apparatus for effecting synchronous pulse generation for use in variable speed serial communications
A method for effecting synchronous pulse generation for use in variable speed serial communications is provided. The method includes the steps of obtaining a communication link speed; generating a...
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7139308 |
Source synchronous bus repeater
A device configured to recover and repeat source synchronous data. In one embodiment, the device is configured to receive source synchronous data via a first interface, recover the received data...
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7136439 |
Adaptive synchronization
A method, apparatus, and system for adaptively synchronizing a sampling clock.
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7136388 |
Clock synchronization system and method for use in a scalable access node
A clock synchronization scheme for use with an access network element having scalable architecture. A point-to-point, high-speed communication link provided between two adjacent banks of the access...
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7136443 |
Sample selection and data alignment circuit
There is disclosed a sample selection and data alignment circuit that is able to recover (retime) a data on a predefined phase of a multiphase clock signal. A plurality of over sampled signals (G 0...
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7136447 |
Clock recovery circuit
A clock recovery circuit for establishing bit synchronization with a received signal. The clock recovery circuit comprises a conventional early-late gate circuit and a loop filter. The loop filter...
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7133483 |
Apparatus and method for a jitter cancellation circuit
The invention produces an output signal that maintains a substantially constant period corresponding to a clock signal. An input signal includes a period that is an integer multiple of the period...
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7133479 |
Frequency synchronization apparatus and method for OFDM systems
A frequency synchronization apparatus and method for OFDM systems. The frequency synchronization apparatus is comprised of a digital mixer, a first synchronizer and a second synchronizer. The...
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7133424 |
Method and device for synchronizing a mobile radio receiver with a time slot structure of a received radio signal
In a method for synchronizing a mobile radio receiver with a radio signal time slot structure a first portion, detected during a first time slot period, and a second portion, detected during a...
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7127536 |
Source-synchronous receiver having a predetermined data receive time
A source-synchronous data receiver includes a storage device for sequentially storing data received from a data source, a data output device for sequentially outputting the data that is stored in...
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7127629 |
Redriving a data signal responsive to either a sampling clock signal or stable clock signal dependent on a mode signal
A method and apparatus for redriving a data signal adjusts a sampling clock signal responsive to the data signal. An embodiment of an I/O cell may include a receiver to receive and redrive a data...
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7123673 |
System and method for transmission of digital information of varying sample rates over a synchronous network
A system for transmitting digital information over a synchronous network includes at least one source node and at least one sink node both coupled with the synchronous network. The source node...
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7123675 |
Clock, data and time recovery using bit-resolved timing registers
A clock recovery method is disclosed wherein the FIFO delay of data words and the phase difference between a data word and a receiver clock are used to time data transmissions from a transmitter....
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7123629 |
Broadband network access device for voice data transmission
In the broadband network access device for transmitting narrowband, low-frequency voice signals and broadband, higher-frequency data signals, the voice data is sampled in the data clock pattern and...
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7123929 |
Method and device for synchronization and identification of the codegroup in cellular communication systems and computer program product therefor
Once slot synchronization has been obtained in a first step, during a second step there is acquired, by means of correlation of the received signal (r) with the synchronization codes, the...
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7123674 |
Reducing latency and power in asynchronous data transfers
Reducing latency and power in the transfer of data between a source and destination domain involves the production of a source-enable signal base on a synchronous-pulse signal. The source-enable...
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