Matches 301 - 350 out of 1456 < 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >
Match Document Document Title
7333548 Phase and frequency drift compensation in Orthogonal Frequency Division Multiplexing systems  
A phase drift compensation scheme for multi-carrier systems. According to the invention, a timing offset compensator is provided to compensate for a timing offset in a current symbol after taking...
7333570 Clock data recovery circuitry associated with programmable logic device circuitry  
A programmable logic device (“PLD”) is augmented with programmable clock data recover (“CDR”) circuitry to allow the PLD to communicate via any of a large number of CDR signaling protocols....
7333576 Digital demodulation device and synchronization detecting method  
A synchronization error occurs when a DTV signal is distorted on a transmission path and this deteriorates demodulation capability. The digital demodulation device and the synchronization detecting...
7330508 Using clock and data recovery phase adjust to set loop delay of a decision feedback equalizer  
In a method and apparatus for communicating data, a decision feedback equalizer equalizes received data to reduce channel related distortion in the received data. An extracted clock signal is...
7330488 System, method, and article of manufacture for synchronizing time of day clocks on first and second computers  
A system, method, and article of manufacture for synchronizing first and second time-of-day clocks on first and second computers, respectively, are provided. The first and second computers have...
7327817 Method and device for providing timing information in a wireless communication system  
A method and a device of providing timing information within a wireless communication system is described. The timing information is extracted from a received transmit signal. The inventive method...
7327816 High resolution synthesizer with improved signal purity  
An automatic test system using a DDS signal generator to create a signal with high spectral purity or a low jitter digital clock. The low jitter clock has variable frequency and is programmed to...
7327815 Method for synchronizing several digital input signals  
The invention relates to a method for synchronizing a plurality of digital input signals which are formed by sampling with the aid of a dedicated operating clock in each case. In order to be able...
7321642 Synchronization symbol re-insertion for a decision feedback equalizer combined with a trellis decoder  
A digital equalizer for interpreting a digital signal including convolutionally encoded symbols and synchronization symbols outside the convolutional code comprises a combined trellis encoder and...
7321648 Drift compensation system and method in a clock device of an electronic circuit  
A drift compensation system includes a first clock phase alignment circuit adapted for providing an output clock signal which is frequency locked to an input reference clock signal; a second clock...
7319712 Orthogonal code generation apparatus, scrambling code generation apparatus and portable radio terminal using such apparatus  
An orthogonal code generation apparatus can generate a sequence of orthogonal codes without having to prestore orthogonal code sequences in a memory, by applying logic operation on a sequence...
7319728 Delay locked loop with frequency control  
A delay locked loop includes a delay line for delaying an input signal generated from an external signal. A delay controller controls the delay line to keep the external and internal signals...
7319729 Asynchronous interface methods and apparatus  
In a first aspect of the invention, a first method is provided for aligning signals from a first receiver located in a first clock domain to a second receiver located in a second clock domain. The...
7317905 Radio-controlled clock and method for gaining time information  
Time signals for controlling a radio clock are transmitted by a transmitter and received by a receiver as amplitude modulated time signals, formed of a multitude of time frames. Each time frame has...
7317773 Double data rate flip-flop  
Method and apparatus for doubling the throughput rate of data transmission on a logic path comprising providing two latches that alternately receive successive bits of the data stream to be...
7315583 Digital subscriber line (DSL) modems supporting high-speed universal serial bus (USB) interfaces and related methods and computer program products  
The present invention provides asymmetric digital subscriber line (ADSL) modems including a discrete multitone (DMT) modem module. The DMT modem module includes a digital signal processor (DSP)...
7313210 System and method for establishing a known timing relationship between two clock signals  
A system and method for establishing a known timing relationship between two clock signals, wherein a first clock signal is operable to clock data transfer operations from a transmitter domain to a...
7313209 Method and arrangement to synchronize a multi-carrier transmission system  
The invention relates to a method to synchronise a multi-carrier transmission system wherein a time misalignment between a transmitter and a receiver is determined through an average of at least...
7313211 Method and apparatus for phase detection  
The present invention relates to a method and apparatus for generating an output signal in dependence on a phase difference between two periodic signals. The present invention is particularly...
7310396 Asynchronous FIFO buffer for synchronizing data transfers between clock domains  
An asynchronous FIFO buffer communicates data between first and second clock domains. The FIFO buffer includes a shift register that accepts and shifts out data at a relatively high output...
7310400 Data recovery device and method  
A data recovery device. The device adjusts a digital signal according to a pulse signal output by a phase-locked loop circuit. The sampling circuit samples each bit of the digital signal five times...
7310398 Symbol synchronizing device  
A symbol synchronization device that enables effective symbol synchronization establishment and synchronization holding for an arbitrary spread code sequence. The device includes (i) a primary...
7310393 Method and apparatus for synchronization of the OFDM systems  
A method and apparatus for the signal synchronization of an orthogonal frequency division multiplexing system includes a delay conjugate multiplication module, a phase processor and an edge...
7308064 Frame synchronization method based on differential correlation information in satellite communication system  
Provided is a frame synchronization method for synchronizing frames with pilot blocks added thereto based on differential correlation information in a satellite communication system. The method can...
7308025 Transmitters providing cycle encoded signals  
In some embodiments, the inventions includes a transmitter including a cycle encoding circuit to receive a data input signal and to provide a full cycle encoded signal in response thereto by...
7308023 Dual function clock signal suitable for host control of synchronous and asynchronous target devices  
A host device in a data communication system provides a dual-function clock/enable signal at a single output port shared by at least one asynchronous target device and at least one synchronous...
7308063 Apparatus, and associated method, for effectuating post-FFT correction of fine frequency offset  
In an orthogonal frequency division multiplexing (OFDM) system, a receiver of an OFDM signal via an air interface defines training symbols to be included in the frame structure of the air interface...
7305023 Receivers for cycle encoded signals  
In some embodiments, the inventions includes a transmitter including a cycle encoding circuit to receive a data input signal and to provide a full cycle encoded signal in response thereto by...
7298806 Method and system for data-aided timing offset estimation for frequency selective fading channels  
The disclosed invention provides a system, a method and a computer program product for timing offset estimation for frequency selective fading channels in wireless communication systems. The...
7292664 Process and device for synchronization and codegroup identification in communication systems of the cellular type  
To obtain frame synchronization and identify the cell codegroup in a cellular communication system (such as a system based upon the standard 3GPP FDD), there are available the synchronization codes...
7292670 System and method for automatically correcting duty cycle distortion  
In accordance with the teachings described herein, systems and methods are provided for automatically correcting duty cycle distortion. A slicer may be used to receive a data input signal and...
7293214 Testable design methodology for clock domain crossing  
A design methodology to debug synchronization of a signal crossing clock domains. A testable synchronization control logic utilizes a programmable register to set parameters to test signals...
7292665 Method and apparatus for reception of data over digital transmission link  
An over-sampled sequence detector operates on sampled data and tracks the detection reliability of the sampled data. The detector separately analyzes sample sequences for different sampling phases...
7287105 Asynchronous-mode sync FIFO having automatic lookahead and deterministic tester operation  
Precise estimation of latency is attained based on identifying that a receive clock is configured to operate only at prescribed available frequencies. A receive buffer circuit includes buffer...
7283601 Timing signal generating system and receiving circuit for transmitting signals at high speed with less circuitry  
A timing signal generating system has a clock signal generating circuit, a synchronizing circuit, a phase code recognizing circuit, and a calibration circuit. The clock signal generating circuit...
7283598 OFDM receiver apparatus  
An OFDM receiver apparatus comprises a receiver to receive an OFDM signal, an estimator to estimate a distortion, a distortion compensator subjecting the sub-carrier to distortion compensation...
7283602 Half-rate clock and data recovery circuit  
A half-rate clock and data recovery (CDR) circuit includes a half-rate phase detector for detecting phases of an input signal and a half-rate clock, a charge pump circuit, a low-pass filter and a...
7280602 Microwave signal edge detector circuit for improved clock recovery  
A signal edge detector circuit is described for the detecting the signal transitions in a stream of microwave signals at a predetermined clock signal rate, particularly for OC-768 data streams....
7280629 Method and apparatus for receiving data based on tracking zero crossings  
Conventional receiver architectures are based on either frequency/phase tracking or oversampling. Both receiver types typically employ sensitive analog circuits, which create noise, consume power...
7280607 Ultra wide bandwidth communications method and system  
An ultra wide bandwidth, high speed, spread spectrum communications system uses short wavelets of electromagnetic energy to transmit information through objects such as walls or earth. The...
7280615 Method for making a clear channel assessment in a wireless network  
A method is provided for performing a clear channel assessment in a wireless network. The method involves first listening for channel energy on a wireless channel. Whatever channel energy is heard...
7280628 Data capture for a source synchronous interface  
Method and apparatus for data recapture from a source synchronous interface. A data signal is obtained via the source synchronous interface. A timing signal is obtained via the source synchronous...
7277519 Frequency and phase correction in a phase-locked loop (PLL)  
In one embodiment, a system for frequency and phase correction in a phase-locked loop (PLL) includes a phase frequency detector, first and second charge pumps respectively generating a first...
7275174 Self-aligning data path converter for multiple clock systems  
A system and method for aligning an input signal ( 24 ) synchronized to a first clock signal ( 22 ) with a second clock signal ( 26 ) The invention includes a mechanism ( 106 ) for generating a...
7274761 Device synchronisation over a network  
A transceiver for operating in a network wherein the transceiver is arranged to synchronize to a time reference common to the network having distinguishable instances, the transceiver containing a...
7274762 Calculation circuit for calculating a sampling phase error  
A calculation circuit for calculating a sampling phase error is provided. According to one aspect, a calculation circuit includes a first delay element chain having serially connected delay...
7272743 Semiconductor integrated circuit  
A circuit according to an embodiment of the present invention comprises a first power supply region supplied with a first power supply voltage, and having a first clock distribution network, a...
7272681 System having parallel data processors which generate redundant effector date to detect errors  
A high assurance processing system includes a plurality of data processors coupled in parallel, a bridge coupled to the plurality of data processors, and an input/output processor coupled to the...
7272200 Phase shifter, phase shifting method and skew compensation system for high-speed parallel signaling  
The invention intends to realize a high accuracy of some picoseconds in skew compensation as well as a downsized circuit scale. A phase shifter using analog circuits that allows a downsized circuit...
7269203 Receiver for receiving a spectrum dispersion signal  
A receiver for the CDMA system, in order to reduce a power consumption during a suspension period of intermittent receiving operation, monitors a suspension period t 1 by means of a low-power...
Matches 301 - 350 out of 1456 < 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >