Matches 251 - 300 out of 1469 < 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >
Match Document Document Title
7408996 Method and apparatus for synchronization of data in a transformer circuit  
A method and apparatus for synchronizing the secondary side to the primary side of a transformer circuit are presented. A preamble which consists primarily of data pulses and inverted power pulses...
7409023 Method and apparatus for effecting synchronous pulse generation for use in serial communications  
A method for effecting synchronous pulse generation for use in serial communications is provided. The method includes the steps of generating a difference signal representing a signal level...
7409022 Synchronizing clocks in wireless personal area networks  
A method synchronizes a transmit clock of a transmitter with a receive clock of a receiver in a wireless communications network. Times t 1 , t 2 , t 3 , and t 4 of the transmit clock corresponding...
7403546 Receiver, sender, method and burst signal  
Known burst signals exchanged between senders and receivers comprise either one syncronisation block followed by a data block or several equidistant synchronisation blocks separated by data blocks,...
7403583 System and method for predictive synchronization for locating interleaving frames and demodulation training sequences  
A system and method for using Psuedo-Noise (PN) phase to determine frame start of a data frame is provided. The system and method includes at least two PN component codes, wherein the at least two...
7403584 Programmable phase interpolator adjustment for ideal data eye sampling  
A clock recovery circuit includes a demodulator which generates in-phase and quadrature signals from a data signal and a phase adjuster which adjusts a phase of the quadrature signal independently...
7400695 System and method for time-marking data  
This invention concerns a system comprising processors ( 2, 3 ) arranged so as to receive and process data arriving at the system and containing time-indicating means ( 11, 17, 21 ) operatively...
7397861 Mapping strategy for OFDM-based systems using H-ARQ  
A wireless communication device, method and system adapted so that, in response to a repeat request indicating a communication signal (because of an error in transmission of the communication...
7397875 Method of synchronising data  
A method of synchronizing data in a communications system includes generating a composite signal comprising a serial stream of data partitioned in one or more frames, and transmitting the composite...
7398411 Self-calibrating time code generator  
Provided is a self-calibrating time code generator and method for generating an accurate time code (e.g., an accurate IRIG waveform). The self-calibrating time code generator includes a...
7394830 System for synchronizing circuitry in an access network  
A master Timestamp Synchronization Circuit (TSC) in a Cable Modem Termination System (CMTS) estimates a master timestamp value for an upcoming time reference. The master TSC sends the master...
7394870 Low complexity synchronization for wireless transmission  
A receiver, system and method for providing symbol timing recovery that allows for inexpensive and low-complexity synchronization for communication systems. A receiver receives a signal including...
7394755 Semi-fixed circuit  
A semi-fixed circuit has a plurality of flip flops connectable in series, a first selector and a second selector, and is capable of operations of a plurality of kinds of scrambler and the like. The...
7394882 Digital communication synchronization system and method thereof  
Disclosed is a synchronization system in digital communication, which comprises a converter for receiving signals from a transmitter, and oversampling a single symbol interval into a plurality of...
7391836 System and method for synchronous clock re-generation from a non-synchronous interface  
A system and method transmits data received at varying frequencies at a fixed data rate. The frequency dependent data and associated data clock signal are received and the frequency dependent data...
7391835 Optimizing synchronization between monitored computer system signals  
One embodiment of the present invention provides a system that optimizes synchronization between monitored signals in a computer system. During operation, the system receives a number of monitored...
7388938 Method for bit-byte synchronization in sampling a data string  
Bit and byte synchronization for sampling and decoding a data string is provided a single data field u. The data string x has pre-pended to it a short string of 1s (ones), followed by u to yield a...
7386079 Seamless clock  
System ( 10 ) comprising at least two units ( 1, 2 ) with clock functionality, the units being coupled to a common system clock line (SCLK), a common internal clock line (ICLK), and a logic bus...
7386082 Method and related apparatus for searching the syncword of a next frame in an encoded digital signal  
A method and apparatus for searching the synchronization signal of a next frame in encoded digital signal without the need of referring to a frame length indication signal. The encoded digital...
7386081 Timing control circuit and method thereof  
A timing control circuit includes a synchronous detecting portion which detects a synchronous pattern data of a received signal which has been demodulated based on a first control signal and...
7382823 Channel bonding control logic architecture  
A design is used for coordinating channel bonding operations of a set of transceivers. The set include a master transceiver and a plurality of first level slave transceivers that perform channel...
7382843 System with a clocked interface  
A system with a transmitter for transmitting digital data via an interface to a receiver. The interface has at least one data line and a clock line. A clock generator supplies a clock signal to the...
7382694 Methods to resolve TSF timer ambiguity of IEEE 802.11e schedule element  
A plurality of methods, computer program product, and apparatus that use a lower 32 bit field of a 64-bit 802.11 TSF timer, so as to encode the reference time instant without the ambiguity as to...
7382847 Programmable sync pulse generator  
A programmable sync pulse generator and sync pulse generation method are operable in a clock synchronizer to effectuate data transfer between first circuitry disposed in a first clock domain and...
7382844 Methods to self-synchronize clocks on multiple chips in a system  
A method of self-synchronizing clocks in a multiple chip system, by assigning one chip as the master chip and the other chips as slave chips. A training signal is sent from master chip to the slave...
7382803 Hybrid high-speed/low-speed output latch in 10 GBPS interface with half rate clock  
A high-speed serial demultiplexer receives over four high-speed serial data lines at a nominal rate of 10 GBPS and demultiplexes the data to 16 lines with a rate of 2.5 GHz each. The demultiplexer...
7382846 Off-symbol correlation technique  
A method of correlating a signal to a synchronization pattern is disclosed. The signal has a waveform with frequency and phase angle components that may be varied, at each repeated signal pulse, to...
7379520 Low jitter phase rotator  
A phase rotator generates an output signal having plurality of possible output phases with reduced phase jitter. The low jitter phase rotator includes a plurality of differential amplifiers...
7379517 Method and apparatus for signaling characteristics of a transmitted signal  
A method and apparatus are provided that allow exploitation of the common mode characteristics of a differential transmission network to provide an additional data signal. Signal (MODE) represents...
7376211 High speed early/late discrimination systems and methods for clock and data recovery receivers  
The present invention facilitates clock and data recovery for serial data streams by providing a mechanism that can be employed to detect and adjust operation and timing of clocks. The invention...
7372930 Method to synchronize data and a transmitter and a receiver realizing said method  
A method to realize synchronization of data (DAT) sent from a transmitter (TX) to the receiver (RX), with a signal (SIG) available in the receiver (RX). The method includes the following steps: in...
7372928 Method and system of cycle slip framing in a deserializer  
A method and system for cycle slip framing is disclosed. The method includes receiving an asynchronous signal and generating a synchronous pulse after receiving the asynchronous signal. The method...
7369634 Training pattern for a biased clock recovery tracking loop  
Some embodiments of the invention provide a biased tracking loop that may include encoded information. Embodiments may comprise a training pattern, utilized in a non-interfering way that allows for...
7369633 Method and apparatus for providing carrier synchronization in digital broadcast and interactive systems  
An approach is provided for supporting carrier synchronization in a digital broadcast and interactive system. A carrier synchronization module receives one or more signals representing a frame that...
7369623 Apparatuses to simultaneously distribute clock signals and data on integrated circuits, interposers, and circuit boards  
A technique is described for simultaneously and synchronously transmitting digital data and a clock signal in a digital integrated circuit, circuit board, or system. The technique is based on the...
7366938 Reset in a system-on-chip circuit  
An electronic device having first circuitry operating in a first clock environment and second circuitry operating in a second clock environment, the first circuitry being arranged to generate a...
7366267 Clock data recovery with double edge clocking based phase detector and serializer/deserializer  
A programmable logic device (“PLD”) is augmented with programmable clock data recover (“CDR”) circuitry to allow the PLD to communicate via any of a large number of CDR signaling protocols....
7366268 Selective data inversion in ultra-wide band communications to eliminate line frequencies  
A method for generating an ultra-wide-band (UWB) having a reduced discrete frequency component defines frame synchronization signal and an inverted frame synchronization signal. As each frame is...
7362833 Dynamic special character selection for use in byte alignment circuitry  
Circuitry for locating the boundaries of bytes in a data stream is provided. The data stream typically has comma or header information that provides an indication of the byte boundaries. When...
7362812 Channel tracking using step size based on norm-1 based errors across multiple OFDM symbols  
A channel tracking module, configured for generating updated equalization coefficients for a frequency equalizer, is configured for determining a digital-based error value between equalized signals...
7362835 Clock generator circuit and related method for generating output clock signal  
The present invention discloses a clock generator circuit for generating an output clock signal. The clock generator circuit includes: a random frequency code generator for generating a frequency...
7362834 Method and device for synchronizing at least one node of a bus system and a corresponding bus system  
Method of synchronizing at least one user of a bus system which is operated with a preselectable system clock period (NTU), a local clock period (LNTU) and a reference clock period (GNTU) being...
7362743 Method and system for receiving an ultra-wideband signal with a self-adapting number of propagation paths  
A method and a system for receiving an ultra-wideband signal with a self-adapting number of propagation paths. The transmitted signal includes, over a symbol time, a series of direct successive...
7359467 Method and apparatus for increasing the quality of the receiver synchronization of QAM or CAP modulated modem connection  
The invention relates to a method and apparatus for improving the quality of receiver synchronization on QAM- or CAP-modulated modem connections having an adaptive linear equalizer. The invention...
7359469 Signal delaying device and method for dynamic delaying of a digitally sampled signal  
A signal delaying device ( 1 ) for the dynamic delaying of a digitally sampled input signal comprises a memory element ( 2 ) and a series-connected interpolation element ( 3 ). According to the...
7356106 Clock and data recovery circuit  
A clock and data recovery (CDR) circuit comprises a phase detector (PD) and a quadrature phase (QP) detector. A frequency detector (FD) is coupled to the PD and QP detector. The FD detects...
7355378 Source synchronous sampling  
There is provided a method of source synchronous sampling, where a first clock signal of a first unit is synchronized to a second signal received from a second unit. The method includes determining...
7352834 Code phase synchronization  
The invention relates to a method for synchronizing the phase of a code available at a receiving unit with the phase of a corresponding code of which samples are received at said receiving unit....
7352836 System and method of cross-clock domain rate matching  
Described are a system and method for providing an interface to synchronize data transfers across clock domains. A first pulse converter receives a request signal in a first clock domain and...
7350092 Data synchronization arrangement  
A data synchronization arrangement is provided for exchanging clocked data between different clock domains running at the same clock frequency but at an arbitrary relative phase shift. An input...
Matches 251 - 300 out of 1469 < 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >