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7602852 |
Initial parameter estimation in OFDM systems
A coarse estimate of a location of an information carrying part of a symbol in a received signal in a telecommunication system is generated. This involves generating correlation values by...
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7599459 |
Receiving apparatus, data transmission system and receiving method
A receiving apparatus receives data sequences, each of which includes plural data blocks, from plural transmission lines, respectively. The apparatus includes plural elastic buffers and a deskew...
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7599309 |
Method and apparatus for managing cell-by-cell demodulation timings of a user equipment in an asynchronous mobile telecommunication system
A method and an apparatus are provided for managing cell-by-cell demodulation timing of an asynchronous user equipment (UE) for demodulating multipath signals, received from a plurality of cells,...
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7599456 |
Input/output data rate synchronization using first in first out data buffers
An input/output data rate synchronization system includes a first data buffer that receives input data at a first rate, that temporarily stores the input data, and that outputs the input data at a...
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7596196 |
Timing recovery in error recovery for iterative detection
A decoding system includes a timing loop for use in error recovery mode operations, in which “fast decode” bit values that are used for timing recovery purposes in the normal modes of operation...
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7593495 |
Method for performing high resolution phase alignment of multiple clocks using low resolution converters
The offset between a reference clock output signal and a target clock output signal are measured during a predetermined period. Based on the measurement, an offset signal is generated. The offset...
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7593500 |
Apparatus for coordinating triggering of analog-to-digital conversions relative to pulse width modulation cycle timing
A pulse width modulation (PWM) generator featuring very high speed and high resolution capability and the ability to generate standard complementary PWM, push-pull PWM, variable offset PWM,...
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7590183 |
Generating signals for transmission of information
A method for generating a signal is presented. The method includes selecting a first set of carrier frequencies that are integral multiples of a first frequency interval, and selecting a second set...
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7590207 |
Modular serial interface in programmable logic device
A serial interface for a programmable logic device can be used as a conventional high-speed quad interface, but also allows an individual channel, if not otherwise being used, to be programmably...
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7590184 |
Blind preamble detection for an orthogonal frequency division multiplexed sample stream
A method for determining a presence of a preamble for an orthogonal frequency division multiplexed (OFDM) complex valued sample stream may include capturing a portion of the OFDM complex valued...
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7590208 |
Circuit and method for generating a timing signal, and signal transmission system performing for high-speed signal transmission and reception between LSIs
A signal transmission system has a plurality of signal lines, a plurality of transmitting circuits, a plurality of receiving circuits, and a timing adjusting circuit. The transmitting circuits are...
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7589586 |
High frequency signal detection circuit
A high frequency signal detection circuit includes an input terminal for a high frequency signal to be detected, a switch transferring the high frequency signal as intermittent ringing signal to a...
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7590397 |
Signal processing apparatus and signal processing method, program, and recording medium
An IC chip allows first communication for performing communication with all of the other IC chips, and second communication for performing communication while restricting communication parties....
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7587013 |
Apparatus for updating gain of loop filter
For updating a gain of a loop filter from a timing error signal, a timing signal estimator generates a current timing signal estimation value from a prior timing error estimation value, a prior...
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7586954 |
Communication system
In a communication system where a terminal operates in clock synchronization with a global time used on a network, a period of time required for establishing clock synchronization when the terminal...
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7587011 |
Digital-data receiver synchronization method and apparatus
Digital data receiver synchronization is provided with composite phase-frequency detectors, mutually cross-connected comparison feedback or both to provide robust reception of digital data signals....
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7587012 |
Dual loop clock recovery circuit
A clock recovery circuit for digital data transmission includes a delay lock loop having a first loop which generates a phase difference signal which is indicative of a quantized phase difference...
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7587014 |
Digital frequency/phase recovery circuit
A digital frequency/phase recovery circuit includes a comparator with hysteresis, a counter, a frequency determiner, a multi-phase clock generator, a transition detector, a phase adjuster, and a...
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7586976 |
Initial ranging detection for OFDMA systems
An initial ranging detection for an orthogonal frequency division multiple access (OFDMA) wireless communication system entails removing data sub-carriers from samples of an OFDMA signal in order...
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7583774 |
Clock synchroniser
A clock synchronizer, for generating a local clock signal synchronized to a received clock signal, is described and claimed, along with a corresponding clock synchronization method. The clock...
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7583720 |
Wireless communication method and apparatus for assigning multi-paths to rake receiver fingers
A wireless communication method and system for assigning multi-paths to Rake receiver fingers. A Rake finger assignment database is established in which multi-path signals are categorized into a...
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7583772 |
System for shifting data bits multiple times per clock cycle
A system and method are used to allow for phase rotator control signals to be produced that rotate bits in the signals more than one step per clock cycle. This can be done through the following...
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7580494 |
Low wander timing generation and recovery
Systems, apparatuses, and methods for low wander timing generation and/or recovery are disclosed here. In one aspect, embodiments of the present disclosure include a communication system for high...
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7580491 |
Quarter-rate clock recovery circuit and clock recovering method using the same
A quarter-rate clock recovery circuit includes a clock generator, a phase interpolation unit, a phase detector, and a controller. The clock generator generates first through fourth clocks having a...
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7580468 |
Synchronization circuits, orthogonal frequency division multiplexing (OFDM) receivers, and related methods and computer program products
Synchronization circuits are provided for orthogonal frequency division multiplexing (OFDM) receivers. The synchronization circuits include a fast Fourier transform (FFT) processor and a...
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7577216 |
Guard interval and FFT mode detector in DVB-T receiver
For determining FFT and GI (guard interval) modes within a receiver, a correlation signal is generated from an in-phase and quadrature (I/Q) stream. An plurality of GI mode division signals are...
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7577219 |
Apparatus for communications
An apparatus for communications includes, a front processor for outputting a digital formatted base band signal with quadrature demodulating a modulated signal; an interpolation processor for...
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7573932 |
Spread spectrum clock generator
A spread spectrum clock generator includes a non-volatile memory to store control codes corresponding to a predetermined delay. A delay circuit receives a control code having a predetermined number...
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7571338 |
Determining a time difference between first and second clock domains
Buffer circuitry receives data to be processed by electronic circuitry using a first clock signal associated with a first clock domain. The buffered data is output using a second clock signal...
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7570721 |
Apparatus and method for multi-phase digital sampling
A method and apparatus for determining a relationship between an input signal frequency and a reference signal frequency is envisioned. The system derives a plurality of internal reference signals...
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7570715 |
Digital signal receiving circuit
A delayed peak detector detects a peak level of an input signal IN at timing lagged behind a peak detector, and a peak difference detector detects a peak difference PLD between a delayed peak level...
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7570684 |
Method for joint time synchronization and frequency offset estimation in OFDM system and apparatus of the same
Embodiments of the present invention include a method for performing joint time synchronization and carrier frequency offset estimation in a wireless communication system, comprising steps of: on a...
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7567629 |
Multiphase clock recovery
The invention represents a parallel and distributed approach to clock recovery based on multiple mutually phase shifted sample clock signals (åS) defining a set of orthogonal clock phases. The...
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7567639 |
Method and apparatus for generating preamble sequence for adaptive antenna system in orthogonal frequency division multiple access communication system
Disclosed is a method and an apparatus for generating a preamble sequence for an adaptive antenna system supporting a space division multiple access in an OFDMA communication system. Particularly,...
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7567101 |
Digital PLL circuit
A frequency comparator compares frequencies of a reference clock and an output clock to output a frequency comparison signal. A frequency variable circuit is composed of a delay circuit, which has...
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7567637 |
Wireless communication system and method with frequency burst acquisition feature using autocorrelation and narrowband interference detection
A wireless communication system is provided that detects a frequency burst (FB) through analysis of the autocorrelation function of received signals. The system can accommodate the relatively large...
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7567643 |
Phase lock loop device
A phase lock loop device further includes a probability shaping device provided between a phase detection device and charge pump and loop filter (CPLF) device. The probability shaping device...
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7567630 |
Data processing device including clock recovery from various sources
A data processing device is described having a first receive data input unit for inputting a first receive data stream into the data processing device, at least one second receive data input unit...
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7564934 |
Digital signal processing of multi-sampled phase
The DSP MSP invention provides an implementation of programmable algorithms for analyzing a very wide range of low and high frequency wave-forms. The DSP MSP comprises a synchronous sequential...
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7564935 |
AGC circuit which is hard to be influenced by level of input signal
Provided is an AGC circuit which is hard to be influenced by the level of an input signal. The AGC circuit includes an amplification element 11 which has an input terminal 11 g for receiving...
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7561582 |
Data reception device
A data reception device having a reception data buffer unit storing a plurality of packets contained in a data packet, a reception data amount measuring unit measuring the data amount stored in the...
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7558354 |
Pilot symbols in communication systems
This invention relates to signal processing in telecommunications, particularly but not exclusively for use in wireless TDMA systems. In particular, the invention concerns methods for use in...
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7558356 |
Providing global positioning system (GPS) timing signals to remote cellular base stations
In a cellular network, a GPS receiver includes circuitry that modulates a global positioning system (GPS) timing pulse signal with a carrier signal and transmits the modulated signal to one or more...
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7558355 |
Syncword detecting circuit and a baseband signal receiving circuit
A predetermined syncword detecting circuit includes a matched-bit-number comparing circuit, a comparing-result-change detecting circuit, a detected-result storing circuit, a total number detecting...
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7558552 |
Integrated circuit and method of generating a bias current for a plurality of data transceivers
Various embodiments of the present invention relate to circuits for and methods of generating a bias current for a plurality of data transceivers on an integrated circuit. According to one...
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7558358 |
Method and apparatus for generating a clock signal according to an ideal frequency ratio
A method and apparatus for generating a clock signal according to an ideal frequency ratio provides flexible and reduced frequency error clock generation. A ratio control number is specified or is...
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7558317 |
Edge calibration for synchronous data transfer between clock domains
Systems and methods of edge calibration for synchronous data transfer between clock domains are disclosed. An exemplary method may comprise comparing a drive clock signal to a receive clock signal,...
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7558345 |
Apparatus and method for synchronizing symbol timing synchronization applicable to orthogonal frequency division multiplexing (OFDM) receiver
An apparatus and method applied to an orthogonal frequency division multiplexing (OFDM) receiver performs symbol timing synchronization by correlation between channel impulse responses. The...
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7555086 |
Plural circuit selection using role reversing control inputs
Data is communicated through two separate circuits or circuit groups, each having clock and mode inputs, by sequentially reversing the role of the clock and mode inputs. The data communication...
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7555590 |
Fast buffer pointer across clock domains
Retiming circuitry for retiming a data signal transmitted from a first environment under control of a first clock signal to a second environment under control of a second clock signal, said first...
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