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7123929 |
Method and device for synchronization and identification of the codegroup in cellular communication systems and computer program product therefor
Once slot synchronization has been obtained in a first step, during a second step there is acquired, by means of correlation of the received signal (r) with the synchronization codes, the...
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7123674 |
Reducing latency and power in asynchronous data transfers
Reducing latency and power in the transfer of data between a source and destination domain involves the production of a source-enable signal base on a synchronous-pulse signal. The source-enable...
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7123678 |
RZ recovery
A data and clock recovery system adapted for use with RZ data. In one embodiment a phase detector provides phase information for low to high data signal transitions only. In another embodiment a...
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7120090 |
Method of determining a timing offset between a first clock and a second clock in a communications network
A system for determining a timing offset between a first clock and a second clock at respective first and second points in a communications network. A series of request signals is transmitted from...
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7120217 |
Phase-locked loop circuit
In a PLL circuit including a voltage-controlled oscillator, a phase detector and a final control element, the final control element contains two separate channels, between the phase detector and...
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7120214 |
Synchronous signal transfer and processing device
A transfer circuit includes a plurality of cascaded latch circuits. Two consecutive latch circuits in the transfer circuit complementarily enter a latching state and a transparent state in response...
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7120814 |
System and method for aligning signals in multiple clock systems
A system and method for aligning an input signal ( 24 ) synchronized to a first clock signal ( 22 ) with a second clock signal ( 26 ). The invention includes a mechanism ( 106 ) for generating a...
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7116737 |
Apparatus for signaling that a predetermined time value has elapsed
The present invention provides an apparatus for signaling that a predetermined time value has elapsed, having a device for acquiring and storing the amplitude value of a clock signal at an...
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7116739 |
Auto baud system and method and single pin communication interface
In an auto baud system and method, the baud rates between two communicating devices are synchronized by timing the transmission of a plurality of bits by counting the cycles of a reference clock....
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7116736 |
Method, system, and program for synchronization and resynchronization of a data stream
Provided is a method, system, and program for providing synchronization in a binary data stream. A binary data stream is received. A synchronization mark having at least one isolated peak is...
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7116735 |
Adaptive equalization apparatus and method
A correlation between a received signal and a sync word signal is calculated. A window signal having a time span which is equal to an equalization range for an adaptive equalizer is defined. A...
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7116746 |
Synchronous clock phase control circuit
A synchronous clock phase control circuit includes a T/8 step phase clock generation unit, a phase selection unit, and four synchronous clock generation units. The T/8 step phase clock generation...
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7116738 |
Data synchronization apparatus and method
Disclosed is a method and apparatus for synchronizing data. In one embodiment, the apparatus includes a first communication link for transmitting first data and a second communication link for...
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7116740 |
Method and system for providing clock signals
Providing clock signals includes receiving a first clock signal at a first clock circuit and at a second clock circuit, where the first clock signal comprises first cycles. A second clock signal is...
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7110376 |
Method and apparatus for improved cell detection
A method and apparatus for improved cell detection in a cellular communication system correlates a received signal with both a primary synchronization signal and a secondary synchronization signal....
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7110483 |
Communication method
In a first microcomputer, a communication function is provided for outputting a data signal having a transmission period Tr that has a relation of Td<Tp/2 with a data time Td, and it sends...
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7110471 |
Radio communication control device which can accurately determine the start point of the standby period timer
The demodulation unit demodulates a received signal. The detection circuit detects the final data contained in a received data stream supplied from the demodulation unit. When detecting the final...
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7106817 |
Communication device having delay information calculating function
A communication device using orthogonal multiplexing carrier method for determining delay information of received radio waves. In this device, a known signal demodulator performs OFDM demodulation...
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7106758 |
Circuit and method for service clock recovery
A method for synchronizing a service clock at a destination node with a service clock at a source node is provided. The method includes receiving data packets from a source node at at least one...
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7106822 |
Bidirectional synchronous interface with single time base
A bidirectional synchronous interface for the reception of a first flow of digital data with a first coding from a communication channel, and for the transmission on the communication channel of a...
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7106820 |
System and method for establishing word synchronization
A phase synchronizer may operate, for example, to establish synchronization with a phase of a received codeword. The phase synchronizer may include, for example, an input shift register, a first...
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7103061 |
Synchronization codeword for interference reduction in a CDMA system
The CDMA communication system according to the invention comprises at least one primary station ( 2 ) and a plurality of secondary stations ( 4 ). The primary station ( 2 ) and the secondary...
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7103128 |
Data synchronization circuit and communication interface circuit
There is provided a data synchronization circuit for synchronizing a (n+1) (n: natural number) bit bus data synchronous with a first clock with a second clock, comprising: a first circuit for...
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7103124 |
Synchronization of nodes
A method and apparatus for adjusting an oscillator in a network for correcting frequency drift is disclosed. Nodes in the network exchange time stamp messages with each other. The time stamp...
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7103125 |
Method and apparatus for effecting synchronous pulse generation for use in serial communications
A method for effecting synchronous pulse generation for use in serial communications is provided. The method includes the steps of generating a difference signal representing a signal level...
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7103126 |
Method and circuit for adjusting the timing of output data based on the current and future states of the output data
A clock synchronization circuit receives an input clock signal along with current and future data signals. The clock synchronization circuit generates a phase shifted clock signal in response to...
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7099422 |
Synchronization of ultra-wideband communications using a transmitted-reference preamble
A method and apparatus of initial synchronization, or acquisition, of time modulated ultra-wideband (UWB) communications uses a transmitted-reference preamble. The method and apparatus require that...
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7100067 |
Data transmission error reduction via automatic data sampling timing adjustment
A data transmission error reduction circuit is formed including a delay circuit, a detection circuit and a control circuit. In one embodiment, the delay circuit includes n delay element and...
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7099421 |
Synchronization signal detector and method
A synchronization (sync) signal detector and associated method detect the occurrence of a known sync signal in a received signal. The known sync signal is generated and correlated with the received...
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7100065 |
Controller arrangement for synchronizer data transfer between a core clock domain and bus clock domain each having its own individual synchronizing controller
A controller arrangement for effectuating data transfer across a clock boundary between a core clock domain and a bus clock domain, wherein the core clock domain is operable with a core clock...
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7095815 |
Receiver and method for initial synchronization of a receiver with the carrier frequency of a desired channel
The invention relates to a receiver and a method for initial synchronization of a receiver with the carrier frequency of a desired channel. It can happen during synchronization that the locally...
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7095816 |
Clock/data recovery circuit
A clock/data recovery circuit used in a receiving apparatus is provided in the circuit including: a voltage control oscillator for generating a clock signal of a frequency of 1/K of a bit rate of...
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7095353 |
Frequency to digital conversion
A technique of processing an input signal having an input signal phase is disclosed. The technique includes determining a number of transitions of the input signal within a period having a start...
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7095818 |
Data transmission process with auto-synchronized correcting code, auto-synchronized coder and decoder, corresponding transmitter and receiver
A data transmission process with auto-synchronised correcting code, auto-synchronised coder and decoder, corresponding transmitter and receiver. According to the invention, synchronisation...
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7092377 |
Bi-directional time slot estimator for wireless communication system
A method of determining a time slot timing based upon an input sequence r(n) is disclosed. The method comprises using a frequency correction channel detector to determine a first time slot end time...
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7092474 |
Linear phase detector for high-speed clock and data recovery
Methods and apparatus for recovering a clock and data from a data signal. A method provides for receiving a clock signal having a first clock frequency and alternating between a first level and a...
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7092456 |
Process for synchronization
A process for synchronization of an input signal (S) involves demodulating ( 5 a ) the input signal (S) according to a particular demodulation method (AM) using a particular signal parameter for...
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7092449 |
High-speed communication system with a feedback synchronization loop
In a communications device having a physical layer device and a processing device connected to the physical layer device, the number of input/output (I/O) ports required for communication between...
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7085336 |
Signal transmission circuit and method for equalizing disparate delay times dynamically, and data latch circuit of semiconductor device implementing the same
A signal transmission circuit and a method equalize differential delay characteristics of two signal transmission lines. A controllable delay unit is connected serially to the second line, so as to...
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7085337 |
Adaptive per-pair skew compensation method for extended reach differential transmission
High speed data transmission schemes often use differential lines to reduce the effect of noise on the data signal. Unfortunately, the signal propagation on the positive and negative lines may be...
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7082547 |
Data signal processing method and data processor implementing independent and asynchronous system and data clocks
A data clock for use in data communication between the connected processors and a system clock for use in data processing within the own processor are made independent and asynchronous in clock...
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7082172 |
Digital signal gating apparatus and method in a pulse receiver system
A digital signal gating method and apparatus of a preprocessor in a detection system wherein the detection system includes a central processing unit, a main memory and a receiver, whereby the...
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7079612 |
Fast bit-error-rate (BER) test
A bit-error-rate (BER) test is a crucial test for wireless devices to pass, since a device with a high BER does not perform at its best. BER tests are both costly and difficult to perform due to a...
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7079611 |
System and method for synchronizing an asynchronous frequency for use in a digital system
A system and method for accurately detecting an asynchronous frequency within a synchronous digital system. The improved system and method preconditions the asynchronous frequency so that it does...
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7079614 |
Method of generating a measure of a mistiming and apparatus therefor
Known apparatus for measuring jitter in a signal under test employ narrowband filters and limiters that have technological limitations when the bit rate of the signal under test is around 40 Gbps....
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7079613 |
Apparatus and method for using training sequences to estimate timing error in a digital signal receiver
An apparatus and method is disclosed for estimating timing error in a digital signal receiver from a difference between an arrival time of a first training sequence and an arrival time of a second...
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7076012 |
Measure-controlled delay circuit with reduced playback error
A timing control circuit for synchronizing an output clock signal with an input clock signal includes a pulse generator, a measure delay array, a measure circuit, and a forward delay array. The...
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7076013 |
Clock synchronization device
A clock synchronization device is disclosed which optimizes clock skew without increasing the number of unit delay cells by using an auxiliary delay circuit when a clock signal of ultra low...
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7075995 |
Three-order sigma-delta modulator
A three-order sigma-delta modulator having a feedback and a feedforward configuration. The three-order sigma-delta modulator includes: an analog-to-digital converter; a digital-to-analog converter;...
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7076212 |
Radio receiving system and synchronization detection method
A weight vector of a precedent frame calculated by a weight vector calculator ( 4 ) and stored in a memory ( 3 ) is applied to a signal received through a plurality of antennas (ANT 1 , . . . ANT n...
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