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6701140 |
Digital receive phase lock loop with cumulative phase error correction and dynamically programmable correction rate
A digital phase lock loop (PLL) for maintaining synchronization with the phase of a received data signal including a preamble and an information-containing data frame, by incrementing a state...
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6700941 |
Digital demodulation apparatus
A digital demodulation apparatus for performing a stable oscillation operation has a simple circuit configuration. The digital demodulation apparatus includes a pulse width counter for measuring a...
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6697609 |
Carrier reproducing apparatus and method of the same
A carrier reproducing apparatus and method enabling stable operation even at a low S/N, wherein, when phase signals are locked and exceed a predetermined value, a tracking circuit generates a...
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6693980 |
Wideband fast-hopping receiver front-end and mixing method
A wideband fast-hopping receiver front-end uses direct digital synthesis (DDS) to provide quadrature LO signals to the front-end's mixers. A DDS circuit stores multiple digital word sequences which...
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6684033 |
Bit rate detection circuit and algorithm for optical networks
A receiver in an optical network with a bit rate detection circuit for automatically detecting input signal data bit rates to automatically adjust the frequency of a voltage controlled oscillator...
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6683493 |
Timing reproducing device and demodulator
In-phase and orthogonal components of a base band signal having a preamble symbol are squared to obtain squared in-phase orthogonal components. Amount of correlation is obtained between the squared...
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6680970 |
Statistical methods and systems for data rate detection for multi-speed embedded clock serial receivers
Methods and systems for data rate detection for multi-speed embedded clock serial receivers are described. In one embodiment, a method of determining a data rate of a high speed serially...
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6678012 |
LNB drift search system for DBS products
The present invention concerns a digital signal tuning apparatus which includes an offset frequency correction system. In the offset frequency correction system, searching for an offset signal...
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6658066 |
Method and apparatus for multiple phase splitting for dual band IQ subharmonic mixer
A method and apparatus are provided for generating first and second modulation signals from a local oscillator signal for quadrature subharmonic modulation of a quadrature amplitude modulated...
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6658065 |
System of and method for reducing or eliminating the unwanted sideband in the output of a transmitter comprising a quadrature modulator followed by a translational loop
A system of and method for reducing or eliminating any unwanted sideband component in the output of a transmitter comprising a quadrature modulator followed by a translational loop. In one...
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6650875 |
Transmitter architecture having a secondary phase-error correction loop including an amplitude reconstruction system
A system for using a translation loop upconverter and power amplifier including a secondary phase-error correction loop uses the output of the upconverter to lock a feedback loop during a time in...
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6647079 |
Surface acoustic wave-based clock and data recovery circuit
In accordance with an aspect of the present invention, a circuit is provided which is configured to recover clock and data streams from an incoming signal. The circuit comprises a multiplexer...
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6646500 |
Integrated circuit having an FM demodulator and method therefor
A digital FM demodulator employs a baseband phase lock loop (BBPLL), which is particularly effective for long range reception, for combining and demodulating a pair of signals represented by the...
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6639952 |
Demodulator synchronization loop lock-in detection circuit
A method for detecting the lock-in of a loop that synchronizes an internal clock on the transmission of value pairs provided by a demodulator. According to the method, a module of a vector that has...
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6631169 |
Apparatus and method for GMSK baseband modulation based on a reference phase to be simplified
The present invention is an apparatus and method for performing a Gaussian Minimum Shift Keying baseband modulation based on a reference phase to be simplified. The invention mainly comprises: a...
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6617932 |
System and method for wide dynamic range clock recovery
A system and method for clock recovery from an input data stream recovers the clock signal in a manner that preserves the signal strength of the input signal. The measure of signal strength,...
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6614841 |
Signal processing apparatus
A reproduced signal is adaptively equalized in an adaptive equalizer after going through an AD converter. The AD converter, the adaptive equalizer, a phase error detector, a phase shifter, a DA...
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6611571 |
Apparatus and method for demodulating an angle-modulated signal
An angle demodulator in which an FM modulated wave is converted into an IF signal (SI) in the form of digital so as the signal is supplied to a Hilbert transformer ( 81 ) and to an outer product...
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6608869 |
Dual-carrier heterodyne for separating orthogonal components of complex amplitude-modulation signals
A method for receiving a modulated carrier wave with asymmetrical upper and lower sidebands, which carrier wave may be suppressed, is described. A first down-converter in the receiver heterodynes...
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6603349 |
Doppler learning phase lock loop for burst demodulator
The present invention is a demodulator and a method of demodulating burst communications. A demodulator ( 100, 200 ) includes a phase angle source ( 18 ), coupled to a current received burst...
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6597754 |
Compensation of frequency pulling in a time-division duplexing transceiver
A carrier-recovery loop for compensating frequency pulling in TDD and TDMA radio transceivers. The digital carrier-recovery loop includes a signal input, a digitally-controlled oscillator (DCO), a...
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6587521 |
Signal estimator and program stored memory medium
A signal estimator is provided that can track a large frequency offset. A received signal distorted in a transmission path is phase-rotated by the phase rotator ( 102 ) and is then estimated by the...
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6580765 |
Apparatus for recovering symbol timing in cap-based high-speed communication system using single-sided prefilter pair
An apparatus for recovering symbol timing in a CAP-based high-speed communication system such as an ADSL or VDSL, using a single-sided prefilter pair, in which timing information is obtained by...
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6577685 |
Programmable digital signal processor for demodulating digital television signals
A phase-lock loop circuit in a demodulator includes a timing recovery block and a carrier recovery block. The demodulator for demodulates a digital signal including symbols. The phase-lock loop...
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6574287 |
Frequency/Phase comparison circuit with gated reference and signal inputs
Disclosed is a frequency-locked loop (FLL), which attempts to bring about frequency and phase synchronization between two signals over the control bandwidth of the loop: a reference signal and a...
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6574288 |
Method and apparatus for adjusting a digital control word to tune synthesized high-frequency signals for wireless communications
A method and apparatus for synthesizing high-frequency signals is disclosed that overcomes integration problem associated with prior implementations while meeting demanding phase noise and other...
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6567479 |
System and method for extracting and compensating for reference frequency error in a communications system
A system for extracting and compensating for reference frequency error adapted for use with a communication system. The system includes a frequency generator for outputting a reference signal of a...
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6559892 |
Video signal transmitter
To provide a video signal transmission apparatus capable of correctly transmitting a digital video signal. A PLL circuit 5 has a first cutoff frequency lower than the frequency of a horizontal...
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6556591 |
Method and apparatus for upstream burst transmission synchronization in cable modems
A system for synchronizing the upstream burst transmission in a cable system to a time specified by the cable head end is disclosed. The system includes a free running counter within a cable modem...
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6553040 |
Method and apparatus for upstream burst transmission synchronization in cable modems
A system for synchronizing the upstream burst transmission in a cable system to a time specified by the cable head end is disclosed. The system includes a free running counter within a cable modem...
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6549596 |
Fully digital phase aligner
A fully digital phase aligner includes a control loop acting upon a delay line comprising at least a cascade of delay cells, each cell being individually configurable to produce one of two...
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6546059 |
Adaptive integrated PLL loop filter
A loop filter in the phase-locked loop includes a capacitor having a specific capacitance value. The loop filter also includes an amplifier coupled to a node of the capacitor. The amplifier...
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6545532 |
Timing recovery circuit in a QAM demodulator
A timing recovery circuit in a QAM demodulator which uses a symbol rate continuously adaptive interpolation filter. The method of interpolation used in the present invention is defined as a...
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6486742 |
Blind coherent combiner and method using coupled phase-lock loops
Coherent combining apparatus and methods that do not require training to adapt combining weights. The approach employed in the present invention uses phase-lock loops to demodulate input signals....
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6483553 |
TV receiver for digital/analog combined use
The combined TV receiver can receive and process an analog broadcasting signal as well as a digital broadcasting signal, and includes a controller determining whether a channel selected by a user...
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6473470 |
Phase-locked loop circuits for communication system
In a phase-locked loop circuit with a signal estimator such as MLSE or DDFSE for correctly detecting and correcting a phase deviation, the phase deviation is held within a predetermined value by...
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6466086 |
Quadrature demodulator with phase-locked loop
A quadrature demodulator applicable to digital communication and digital broadcast is provided, which simplifies the circuit configuration of a quadrature demodulator section and which reduces the...
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6466270 |
Phase locked loop circuit and method of controlling jitter of OSD characters
The phase locked loop circuit according to the present invention is configured such that the CPU changes the time constant of the variable LPF filter to an optimum value in accordance with the...
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6466630 |
Symbol synchronization in a continuous phase modulation communications receiver
Symbol synchronization in a continuous phase modulation receiver is achieved by calculating an arctangent function of a digital sample of the output of a quadrature demodulator. This signal is...
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6433830 |
Off-air phase lock technique
The proposed phase lock technique uses various feedback loops to lock the frequency and phase of a CATV modulator output signal to that of an off-air signal without directly measuring the output...
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6415004 |
Phase detector, timing recovery device using the same, and a demodulator using the timing recovery device
In the present invention, the amplitude subtracting type of phase detector of the timing recovery section outputs a difference γ i of a synthesized amplitude deviation at ½ of a symbol time. The...
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6411665 |
Phase locked loop clock extraction
A clock recovery circuit includes a phase locked loop in which the control voltage of a voltage controlled oscillator is controlled by a loop filter driven by the output of a phase comparator....
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6411660 |
Device for reducing lock-up time of Frequency synthesizer
A device for reducing a lock-up time in a digital cordless telephone. The telephone includes a first frequency synthesizer for generating a reference frequency, a receiver having a first mixer for...
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6411658 |
Demodulation device
A demodulation device having a demodulating circuit that conducts the primary demodulation of received modulation wave, and a carrier recovery circuit that regenerates a carrier from demodulation...
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6404825 |
Digital radio receiver lock detector
A digital radio tuner lock detector receives an in-phase (I) data signal and a quadrature (Q) data signal. The lock detector processes these signals to compute a data signal power estimate and...
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6393073 |
Method of frequency offset estimation and correction for adaptive antennas
A method of frequency offset estimation and correction for adaptive antennas comprises receiving in a processor samples of a data set having a training data sample sequence. A batch least squares...
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6389548 |
Pulse run-length measurement for HF data signal by dividing accumulated phase difference between first and second zero-crossings by single-cycle range using multiple cycle range sawtooth waveform
A system and method for accurately measuring a pulse run length in a high frequency (HF) data signal while utilizing a low analog-to-digital conversion (ADC) sampling rate. Four bits are added to...
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6385262 |
Method and apparatus for changing the channel bandwidth that is receivable in a radio receiver
The present invention relates to an arrangement ( 1 ) and a method in a receiver in a multi-mode mobile radio (m), wherein the intention is to design the receiver so that it uses the same hardware...
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6370188 |
Phase and frequency offset compensation in a telecommunications receiver
A modem ( 55 ) including receive circuitry ( 30 ) implemented by way of a digital signal processor ( 32, 32′ ) is disclosed. The receive circuitry ( 30 ) operates according to a receive clock...
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6366574 |
Method and device for recovering synchronization on a signal transmitted to a mobile-telephone receiver
Device for recovering synchronization on a signal transmitted to a mobile-telephone receiver, including phase-estimator means ( 47, 49 ) for the absolute value (ABS) and the sign (SIGN) of the...
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