Matches 101 - 150 out of 368 < 1 2 3 4 5 6 7 8 >
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6922356 Method of operation for a programmable circuit  
A programmable circuit and its method of operation are disclosed in which a transistor is used as a programmable element. The transistor may be programmed to one of two different gate threshold...
6922349 Complementary two transistor ROM cell  
A method and structure for a read only memory (ROM) cell array has the first drain of a first transistor connected to a true bitline and a second drain of a second transistor connected to a...
6920626 Method for re-encoding a decoder  
A command user interface with via mask programmability includes a decoder with transistors selectively coupleable to one of an input or its complement. This is accomplished in one way by making...
6920058 Semiconductor memory device  
The present invention prevents a reading operation margin from being decreased due to a current injected into a selected bit line after passing through an unselected bit line in a memory cell array...
6908036 Display and record medium and information writer  
A display and record medium includes a digital information record section, which is implemented as an IC memory and can record record information in noncontact, and an information display section...
6906942 Programmable mask ROM building element and process of manufacture  
A semiconductor memory component such as a mask-programmable ROM component, has two memory cell transistors adjacent to each other in one column of a memory cell field. First and a second...
6907393 Methods for screening candidates for artificial promotors  
The present invention provides methods for selecting artificial promotor candidates that reduce the number of promotors required to be evaluated by actual experimentation when designing artificial...
6903957 Half density ROM embedded DRAM  
A half-density ROM embedded DRAM uses hard programmed non-volatile cells and unprogrammed dynamic cells. By hard programming either a first or second memory cell in a pair of cell, different data...
6895337 Method of identifying genomic rearrangements  
Methods, computer program products and systems are provided for detecting large genomic rearrangements based on unphased genotype data obtained using common genotyping techniques that do not...
6888740 Two-transistor SRAM cells  
A two-transistor SRAM cell includes a first FET. The first FET is an ultrathin FET of a first polarity type and includes a control electrode, a first load electrode and a second electrode. The...
6885585 NROM NOR array  
A NOR array includes a first plurality of word lines, a second plurality of bit lines and a third plurality of common lines. Each word line connects to the gates of a row of nitride read only...
6879506 Non-volatile read-only memory modifiable by redefinition of a metal or via level  
A memory element in an integrated circuit includes several levels of conductive materials separated by insulating levels, each of which is capable of being crossed by conductive vias of an...
6879509 Read-only memory architecture  
The present invention provides a read-only memory (ROM) architecture. An exemplary ROM array includes a plurality of columns, a plurality of rows, a first plurality of transistors or other switches...
6867995 Read only memory configuration to reduce capacitance effect between numbers of bit lines  
A read only memory device includes multiple word lines, a first and second main bit line GL (n) and BL (n), sub-bit lines SB 1 (n) to SB 4 (n), selection switches MB 1 (n) to MB 4 (n), and...
6865100 6F2 architecture ROM embedded DRAM  
A read only memory (ROM) embedded dynamic random access memory (DRAM) has a 6F 2 architecture and uses isolation gates as hard shorting connections for ground or supply voltage connections to...
6857054 Write-once memory storage device  
The present disclosure relates to a write-once storage device. In one arrangement, the storage device comprises write-once memory adapted to store data files, re-writable memory that contains a...
6850427 Single transistor differential ROM  
A single transistor memory storage element has a transistor contact connected to only one of two bitlines to program a logical value for the respective bit, pulling the connected bitline away from...
6836428 Semiconductor memory device including Shadow RAM  
There is provided a semiconductor memory device for preventing an increase of a cell area of a Shadow RAM comprising a portion of an SRAM memory cell and a ferroelectric capacitor connected to a...
6826073 Combination of SRAM and MROM cells  
A new memory cell combination is disclosed. It includes a static random access memory (SRAM) unit and a mask read only memory (MROM) unit. The prior art separates the two memory units in different...
6826070 Read only memory(ROM) cell, program method of ROM cell, layout method of ROM cell, and ROM device comprising ROM cell  
A read only memory (ROM) cell, a method for programming a ROM cell, a method for forming a layout of a ROM cell, and a ROM device including ROM cells are disclosed. The ROM cell includes a gate...
6822889 Read only memory (ROM) and method for forming the same  
A read only memory (ROM) and method for forming the same. A first programming method comprises adjusting threshold voltage of ROM cell by Vt implantation and oxidation. In this programming method,...
6814297 Method and arrangement for controlling access to EEPROMs and a corresponding computer software product and a corresponding computer-readable storage medium  
The invention relates to a method and an arrangement for controlling access to EEPROMs' and to a corresponding computer software product and a corresponding computer-readable storage medium, which...
6809948 Mask programmable read-only memory (ROM) cell  
A multi-bit programmable memory cell is provided that includes an access transistor and a plurality of N anti-fuse elements. The access transistor has a source coupled to a source line and a gate...
6809982 Defective cell remedy method capable of automatically cutting capacitor fuses within the fabrication process  
A method is disclosed for remedying defective cells that enables automatic cutting of capacitor fuses as part of the fabrication process. A comparison circuit determines whether defective cells are...
6804136 Write once read only memory employing charge trapping in insulators  
Structures and methods for write once read only memory employing charge trapping in insulators are provided. The write once read only memory cell includes a metal oxide semiconductor field effect...
6791858 Power reduction in CMOS imagers by trimming of master current reference  
A CMOS imager has a programmable current multiplication stage provided between a master current reference and the analog circuitry. The master current of each chip can be stored on-chip, for...
6785167 ROM embedded DRAM with programming  
Programming efficiency of a read only memory (ROM) embedded dynamic random access memory (DRAM) is improved by programming only one polarity of bits in non-volatile cells of the ROM embedded DRAM,...
6775171 Method of utilizing voltage gradients to guide dielectric breakdowns for non-volatile memory elements and related embedded memories  
A method and related embedded memories are disclosed for utilizing voltage gradients to guide dielectric breakdowns for non-volatile memory elements. Non-volatile memory cells and associated...
6738280 Read only memory  
N-channel MOS transistors are connected to bit lines so as to correspond to the data to be read out. A constant current outputting circuit uses an off leakage current of load transistors similar to...
6690597 Multi-bit PROM memory cell  
A memory cell comprises at least two antifuses in series with a diode. Each antifuse expresses a different resistance from the others when blown, and each requires an escalating programming voltage...
6681186 System and method for improving the accuracy of DNA sequencing and error probability estimation through application of a mathematical model to the analysis of electropherograms  
A system and method for improving the accuracy of DNA sequencing and error probability estimation through application of a mathematical model to the analysis of electropherograms. The method...
6678186 Row decoded biasing of sense amplifier for improved one's margin  
A structure and method to improve sense amplifier operation in memory circuits is provided. An illustrative method of the present invention includes taking the predecoded the row address signals...
6674661 Dense metal programmable ROM with the terminals of a programmed memory transistor being shorted together  
A metal programmable ROM includes a memory cell array having a depth defined by a plurality of wordlines and a width defined by a plurality of bitlines. In addition, a group of memory cells are...
6671216 Method and apparatus to conditionally precharge a partitioned read-only memory with shared wordlines for low power operation  
A ROM or other memory may include two or more partitions and a precharge circuit. Each of the partitions may be coupled to separate sets of output conductors, to which the precharge circuit may be...
6671627 Method and computer program product for designing combinatorial arrays  
A greedy method for designing combinatorial arrays. An array of reagents are initially selected from a list of candidate reagents in a combinatorial library. The reagents in the array that maximize...
6665769 Method and apparatus for dynamically masking an N-bit memory array having individually programmable cells  
Disclosed is a method utilizing dynamic masking for efficiently programming an N-bit memory array and, more generally, for mapping successive subsets of data segments into a succession of N-bit...
6662150 Apparatus and method for recording and/or reading program history  
An integrated circuit, apparatus and method is provided for programming manufacturing information and software program information upon non-volatile storage elements on the integrated circuit. The...
6650579 Semiconductor device having test and read modes and protection such that ROM data reading is prevented in the test mode  
A semiconductor device having a test mode and a read mode is provided. This semiconductor device includes a ROM and a control circuit. When a predetermined condition is satisfied, the control...
6636434 Multibit memory point memory  
A ROM including a set of memory points arranged in rows and columns, in which each memory point, formed of a single controllable switch, memorizes an N-bit information, with N>=2. Each column...
6625546 Structure identification methods using mass measurements  
Methods of identifying predicted or actual structures of members of a chemical or physical library are provided. The methods provide for the direct identification of compound structure following...
6618311 Zero power fuse sensing circuit for redundancy applications in memories  
An invention is provided for a fuse state sensing circuit that senses the state of a fuse, which is coupled between a ground rail and a fuse state sensing node. The fuse state sensing node...
6618295 Method and apparatus for biasing selected and unselected array lines when writing a memory array  
A passive element memory array preferably biases selected X-lines to an externally received V PP voltage and selected Y-lines to ground. Unselected Y-lines are preferably biased to V PP minus a...
6618282 High density ROM architecture with inversion of programming  
A ROM system which provides for reduced size and power consumption. This ROM systems allows for inverting the programming and sensing of information in bit cells of the ROM to reduce the number of...
6611767 Scanned image alignment systems and methods  
Systems and methods for aligning scanned images are provided. A pattern is included in the scanned image so that when the image is convolved with a filter, a recognizable pattern is generated in...
6600673 Compilable writeable read only memory (ROM) built with register arrays  
A method and structure for a pair of read only memory (ROM) cells having a first latch and a second latch connected to the first latch. The first latch and the second latch behave as master and...
6597598 Resistive cross point memory arrays having a charge injection differential sense amplifier  
A data storage device that includes a resistive cross point array of memory cells, a plurality of word lines, and a plurality of bit lines, and a sense amplifier that utilizes an injection charge...
6574129 Resistive cross point memory cell arrays having a cross-couple latch sense amplifier  
A data storage device is disclosed that includes a resistive cross point array of memory cells, a plurality of word lines, and a plurality of bit lines, and a sense amplifier that utilizes a...
6564151 Assigning protein functions by comparative genome analysis protein phylogenetic profiles  
A computational method system, and computer program are provided for inferring functional links from genome sequences. One method is based on the observation that some pairs of proteins A′ and...
6545898 Method and apparatus for writing memory arrays using external source of high programming voltage  
A passive element memory array preferably biases selected X-lines to an externally received V PP voltage and selected Y-lines to ground. Unselected Y-lines are preferably biased to V PP minus a...
6545899 ROM embedded DRAM with bias sensing  
A ROM embedded DRAM that provides ROM cells that can be programmed to a single state. Bias techniques are used to read un-programmed ROM cells accurately. Sense amplifier circuitry can be offset in...
Matches 101 - 150 out of 368 < 1 2 3 4 5 6 7 8 >