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7345701 Line buffer and method of providing line data for color interpolation  
A line buffer and a method of providing data to a 3×3 line interpolation processor using the line buffer in an image processing system, such as a digital camera, includes a readable and writable...
7317780 Shift register circuit  
A shift registers circuit having a series of cascading shift registers comprises a first transistor coupling to an output signal of a pre-stage shift register, a second transistor coupling to the...
7310260 High performance register accesses  
The use of a bus clock is eliminated in communication between a cpu, or mpu, and a register block. The communication between the cpu/mpu and the register block is made combinatorial, such that the...
7256484 Memory expansion and chip scale stacking system and method  
The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve PWB or other board surface area. In another aspect, the invention provides a lower capacitance...
7177421 Authentication engine architecture and method  
Provided is an architecture (hardware implementation) for an authentication engine to increase the speed at which multi-loop and/or multi-round authentication algorithms may be performed on data...
7174014 Method and system for performing permutations with bit permutation instructions  
The present invention provides permutation instructions usable in a programmable processor for solving permutation problems in cryptography, multimedia and other applications. PPERM and PPERM 3 R...
7154984 FIFO-register and digital signal processor comprising a FIFO-register  
A FIFO-register ( 10 ) according to the invention comprises a sequence of register cells ( 10.1, . . . ,10 .m), which register cells have a data section ( 40 ) and a status section ( 30 ). Data...
7120041 Memory device with programmable parameter controller  
The present invention relates to a memory device having the capability of controlling a characteristic parameter including a register controller including a nonvolatile memory unit for storing data...
7092301 Controller and method for writing data  
The present invention provides a controller that can write an operation program for a control circuit to a memory and a method for writing data, while suppressing an increase in circuit area and an...
7092272 Mechanical memory  
A first-in-first-out (FIFO) microelectromechanical memory apparatus (also termed a mechanical memory) is disclosed. The mechanical memory utilizes a plurality of memory cells, with each memory cell...
7057946 Semiconductor integrated circuit having latching means capable of scanning  
Circuits have a certain function. A plurality of first registers are connected in series, and shift stored data to respective adjacent registers in sequence. A plurality of second registers are...
7038965 Pointer generator for stack  
The present invention discloses a pointer generator which generates pointer values for a stack (LIFO memory). The pointer generator includes a selection input terminal and a bi-direction linear...
6987686 Performance increase technique for use in a register file having dynamically boosted wordlines  
For increasing the performance of a register file that is constructed to include dual-V t bitlines or single-V t bitlines. A boost of the drive signal for one of the transistors of a bitline...
6948030 FIFO memory system and method  
A FIFO memory system for multiple input channels, has a channel control logic coupled to a channel input signal. A pointer and flag logic block is coupled to an output of the channel control logic....
6930903 Arrangement of integrated circuits in a memory module  
Integrated circuits utilizing standard commercial packaging are arranged on a printed circuit board to allow the production of 1-Gigabyte and 2-Gigabyte capacity memory modules. A first row of...
6930900 Arrangement of integrated circuits in a memory module  
Integrated circuits utilizing standard commercial packaging are arranged on a printed circuit board to allow the production of 1-Gigabyte and 2-Gigabyte capacity memory modules. A first row of...
6879526 Methods and apparatus for improved memory access  
A memory access scheme employing one or more sets of shift registers interconnected in series to which data may be loaded from or written into one or more memory devices. That is, data from the...
6873534 Arrangement of integrated circuits in a memory module  
Integrated circuits utilizing standard commercial packaging are arranged on a printed circuit board to allow the production of 1-Gigabyte and 2-Gigabyte capacity memory modules. A first row of...
6859844 Electro-optically connected multiprocessor configuration including a ring structured shift-register  
A computer system comprises a plurality of modules and a shift register having a plurality of slots connected in series, wherein each of the plurality of slots is coupled to one of the plurality of...
6842397 Clock-synchronous semiconductor memory device  
A semiconductor device comprises a memory cell array, a control section and a latency setting circuit. The control section configured to receive a clock signal and a control signal, and configured...
6816430 Device for storage of multiport data, particularly for an arithmetic and logic unit of a digital signal processing processor  
The data storage device includes several registers that can be addressed by address words, and connected to p output ports through connections that can be configured in response to address words of...
6804743 Two step memory device command buffer apparatus and method and memory devices and computer systems using same  
A command buffer for use in packetized DRAM includes a two stage shift register for shifting for sequentially storing two of four 10-bit command words in each packet. After the first two words of...
6785389 System for bitstream generation  
A bitstream generator including a plurality of linear feed shift registers (LFSRs) operative to generate a bit stream and including: at least a first LFSR operative, when assigned as a generator...
6751113 Arrangement of integrated circuits in a memory module  
Integrated circuits utilizing standard commercial packaging are arranged on a printed circuit board to allow the production of 1-Gigabyte and 2-Gigabyte capacity memory modules. A first row of...
6713778 Register setting method and semiconductor device  
A register setting method which facilitates writing of change information into a register for storing operation condition information that defines the operation of a device. The method includes the...
6711494 Data formatter for shifting data to correct data lanes  
A data formatter includes a shift register and a pointer manager. The shift register receives data from a providing RAM and shifts that data in response to reading data from the providing RAM and...
6639850 Semiconductor integrated circuit having latching means capable of scanning  
A plurality of first registers are connected in series, and shift stored data to respective adjacent registers in sequence. A plurality of second registers are connected in series, and shift stored...
6628539 Multi-entry register cell  
A multi-entry register file cell includes multiple memory elements. A value stored in each of the multiple memory elements may be individually read from the register file cell in response to...
6622204 Content-addressable memory with cascaded match, read and write logic in a programmable logic device  
An apparatus comprising one or more memory blocks in a programmable logic device. The memory blocks may be configured as content-addressable memory having arbitrarily adjustable tag and data widths.
6577524 Memory structures having selectively disabled portions for power conservation  
An architecture for registers and/or memory may provide a selectively disable payload portion. The architecture induced energy conservation. The architecture may include two or more payload...
6525973 Automatic bitline-latch loading for flash prom test  
A one-shot system for loading a bitline shift register with a typical test pattern is described. Each bitline latch within the bitline shift register is augmented with a one-shot circuit that may...
6473326 Memory structures having selectively disabled portions for power conservation  
An architecture for registers and/or memory may provide a selectively disable payload portion. The architecture induced energy conservation. The architecture may include two or more payload...
6445825 Apparatus and method of generating compressed data  
Compression and encoding sections ( 311 ( 1 ), 311 ( 2 ) and 311 ( 3 ) compress and encode input signals VS, AS and SS separately to generate compressed data. A SCSI interface ( 32 ) outputs...
6438017 Read/write eight-slot CAM with interleaving  
M parallel datastreams are interleaved into a serial bitstream and shifted into a staging register, so that bit zeros of all datastreams shift in first and bit (X-1)s last. All bits of the Mth...
6374313 FIFO and method of operating same which inhibits output transitions when the last cell is read or when the FIFO is erased  
A FIFO is operated so no changes occur on an output thereof in response to (1) only one stage of the FIFO having a signal stored therein when a read command is supplied to the FIFO exclusively of a...
6343041 Semiconductor integrated circuit  
The semiconductor integrated circuit comprises a parallel-serial converter for converting parallel data read from memory cells into serial data and a switch control circuit for receiving a control...
6298002 Memory structures having selectively disabled portions for power conservation  
An architecture for registers and/or memory may provide a selectively disable payload portion. The architecture induced energy conservation. The architecture may include two or more payload...
6226698 Method and apparatus for dynamically calculating degrees of fullness of a synchronous FIFO  
An interface circuit, coupled between a first circuitry that is synchronous to a first clock (sclk) and a second circuitry that is synchronous to a second clock (mclk), for transferring data...
6215728 Data storage device capable of storing plural bits of data  
Disclosed is a data storage device capable of storing plural bits of data using one storage circuit which can hold two signal levels. The data storage device storing the plural bits of data...
6198650 Semiconductor memory device and data output buffer thereof  
It is disclosed a semiconductor memory device and data output buffer thereof in which an area of a layout can be optimized. The semiconductor memory device includes a plurality of memory cell array...
6175518 Remote register hierarchy accessible using a serial data line  
Apparatus and method for accessing numerous remote registers on an integrated circuit chip using a minimum of interconnect traces. Plural primary nodes are configured in series along a serial data...
6115280 Semiconductor memory capable of burst operation  
A semiconductor memory for operating in burst mode. The memory has a memory cell array divided into a plurality of memory blocks, a plurality of (e.g., 2) output registers each including a...
6031390 Asynchronous registers with embedded acknowledge collection  
An asynchronous register with embedded acknowledge collection is disclosed. The asynchronous register includes a data threshold circuit for generating data or NULL values at an output signal line...
6005820 Field memories  
A field memory having a distributed architecture is disclosed and in particular a memory arranged in block, wherein each block stores a bit or bits of said word, said bits having a predetermined...
5996043 Two step memory device command buffer apparatus and method and memory devices and computer systems using same  
A command buffer for use in packetized DRAM includes a two stage shift register for shifting for sequentially storing two of the four 10-bit command words in each packet. After the first two words...
5991186 Four-bit block write for a wide input/output random access memory in a data processing system  
A data processing system includes a data processor and a random access memory arranged with plural memory planes. Each memory plane includes N memory arrays; N serial registers, each serial...
5983315 System and method for establishing priorities in transferring data in burst counts from a memory to a plurality of FIFO stages, each having a low, intermediate, and high region  
Each of a plurality of FIFO has (1) a low region indicating a minimum number of words for FIFO storage, (2) a burst count indicating the number of words involved in each transfer to such FIFO and...
5978295 Sequential access memories  
A sequential access memory comprises N register elements each storing an information bit. These N register elements are divided into P groups each comprising L elements. In a first phase of...
5872738 Semiconductor integrated circuit device for enabling easy confirmation of discrete information  
A semiconductor integrated circuit device including a logic area for executing logical operation and a history holding circuit for managing discrete information concerning respective device, the...
5806084 Space saving method and floor plan for fabricating an integrated circuit comprising a high density buffer memory  
A space saving method and floor plan for fabricating an integrated circuit comprising a high density buffer memory. The method and floor plan allow for a significant reduction in the physical area...
Matches 1 - 50 out of 247 1 2 3 4 5 >