Matches 51 - 100 out of 247 < 1 2 3 4 5 >
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5801981 Serial access memory with reduced loop-line delay  
According to one aspect of the invention, a serial access memory has multiple shift registers that are clocked simultaneously for designating column addresses. Each shift register shifts an...
5764570 Current detecting circuit  
A reading circuit for a multibit register has a differential stage that is configured as an output latch by one of two control phases required by the circuit after the discrimination phase of a...
5633829 Serial access memory device capable of controlling order of access to memory cell areas  
A serial access memory device is disclosed in which order of access to writing and reading memory cell columns can be controlled. A writing column selecting circuit and a reading column selecting...
5630091 High density buffer architecture and method  
A buffer memory architecture, method, and chip floor plan allows for significant reduction in the physical area required for a buffer memory of any given size in a microelectronic device. Buffer...
5625594 Digital video memory  
A digital video memory circuit. The circuit includes a DRAM for storing thereto and reading data therefrom, a register group having registers for holding data to be written to and read from the...
5612964 High performance, fault tolerant orthogonal shuffle memory and method  
A high performance fault tolerant orthogonal shuffle memory comprising a plurality of memory cells arranged to form a two-dimensional array of rows and columns. Each memory cell includes a data...
5600815 High density buffer memory architecture  
A buffer memory architecture, method, and chip floor plan allows for significant reduction in the physical area required for a buffer memory of any given size in a microelectronic device. Buffer...
5550780 Two cycle asynchronous FIFO queue  
A two-cycle asynchronous first-in/first-out (FIFO) device has a plurality of queue registers for holding data, and control cells coupled to the queue registers for controlling data transfer into...
5504913 Queue memory with self-handling addressing and underflow  
The present invention reduces the overhead commonly associated with computer queues by not requiring direct addressing of each location in the queue and by not requiring specialized underflow...
5485597 A CCD array memory device achieving high speed accessing by writing and reading data through a cache memory  
A memory device for storing analog or multilevel data which is easy to produce and of a small scale. The memory device according to the present invention circulates data between a plurality of...
5473756 FIFO buffer with full/empty detection by comparing respective registers in read and write circular shift registers  
A method and apparatus for generating control signals for a high speed First In First Out (FIFO) buffer. Moreover, the present invention limits the instances where signal glitches may occur. A...
5469449 FIFO buffer system having an error detection and resetting unit  
A FIFO buffer system has an error detection and resetting unit for resetting the FIFO buffer system at the occurrence of errors therein. The system comprises M number of data storage circuits...
5469400 Semiconductor memory device using serial pointer  
A FIFO memory device using a serial pointer consists of first second memory cell arrays, a row decoder for selecting a word line first and second write registers for storing data, each write...
5448524 Semiconductor memory device  
An object is to enable a semiconductor integrated circuit device to perform the second action, without waiting for the first action to finish after the first action starts. Aside from a resistor...
5430687 Programmable logic device including a parallel input device for loading memory cells  
A device for configuring portions of an array of memory cells for a programmable logic device comprises a data register, a plurality of shift registers and a control unit. The data are loaded into...
5416745 Parallel data transfer circuit  
A parallel data transfer circuit wherein processing at a data transfer source circuit is simplified to reduce the time required for transfer and a data storage area of a data transfer destination...
5406518 Variable length delay circuit utilizing an integrated memory device with multiple-input and multiple-output configuration  
The present invention discloses an apparatus for receiving an ordered sequence of input data and for delaying the output of a delay output item by a variable-length delay-time. The apparatus...
5373464 CCD array memory device having dual, independent clocks of differing speeds  
The present invention provides a memory device for preventing data circulating on a plural number of linear CCD array from being corrupted, for accessing data at a high speed, and for reducing the...
5343435 Use of a data register to effectively increase the efficiency of an on-chip write buffer  
Using a separate data register effectively increases the efficiency of an on-chip write buffer implemented as a FIFO structure. The separate register holds the output data during write cycles,...
5331598 Memory control device  
A memory control device for controlling writing and reading data in and from a line memory made up of a plurality of FIFO memories. Writing clocks are circularly applied to the plurality of FIFO...
5325329 Dual port memory effecting transfer of data between a serial register and an arbitrary memory block  
A plurality of transfer bit lines each extend longitudinally across a memory array block. Transfer switch circuits are disposed between the transfer bit lines and a serial register. Transfer switch...
5321387 Associative storage for data packets including asynchronous, self-running shift register transmission paths  
An associative storage comprises two data transmission paths each of which includes a self-running shift register formed in loop fashion. In the respective data transmission paths, data packets...
5319598 Nonvolatile serially programmable devices  
An integrated circuit including a serial interface (12) having a nonvolatile memory (30) coupled to a and configuration of circuit boards and entire systems. A configurable circuits (10) containing...
5305253 Zero fall-through time asynchronous fifo buffer with nonambiguous empty-full resolution  
A First In First Out shift register memory system (10) with a plurality of memory word registers (50) having data inputs connected to a common data-in bus (16), and a plurality of data outputs...
5291457 Sequentially accessible non-volatile circuit for storing data  
A sequentially accessible, non-volatile data storage circuit for generating constants includes a logic array for non-volatile storage of programmed data words and a recirculating shift register for...
5267191 FIFO memory system  
The subject invention is a FIFO memory system and method for buffering data between two data busses. The system comprises a RAM memory, write and read pointer registers, an offset generator, a...
5262996 FIFO module  
A FIFO is formed from a plurality of modules each of which comprises a memory section and a control section. A FIFO of arbitrary size can be constructed simply by connecting a desired number of...
5220529 One-chip first-in first-out memory device having matched write and read operations  
A write operation is performed by using a sequentially-incremented write address upon a first-in first-out memory device, and a read operation is performed by using a sequentially-incremented read...
5195055 Serial data input circuit for the shifting-in of variable length data  
A serial data input circuit of this invention which, at the time of inputting of serial data, stores a predetermined signal represented in the bit outputted from the output side of the shift...
5193153 System for detecting overwriting of data in a buffer memory, particularly for a data switch  
Information concerning the access to a first-in first-out buffer memory for reading and writing operations is indicated by the use of two supplemental memories which provide availability and...
5177704 Matrix transpose memory device  
A digital storage device is provided that includes a storage unit having a plurality of word storage locations, each of the word storage locations being coupled to a corresponding read enable line...
5175832 Modular memory employing varying number of imput shift register stages  
A memory including several modules with each module receiving at the input requests coming from a processor and furnishing at the output the responses to these requests. The requests are...
5168463 Shift register apparatus for storing data therein  
An apparatus for storing digital data includes a clock pulse source and plural serial shift register stages storing data bits. Digital data signals, each having plural databits, are coupled to and...
5117388 Serial input/output semiconductor memory  
A semiconductor memory comprises a memory cell array which includes a plurality of memory cells respectively connected to one of a plurality of word lines and to one of a plurality of bit lines, a...
5097442 Programmable depth first-in, first-out memory  
A first-in, first-out memory (10) can store a programmable number of data words at respective address locations within a memory (76). A read address generator (50, 58) generates a read pointer for...
5088061 Routing independent circuit components  
A method and apparatus are disclosed for storing and accessing information of both asynchronous and synchronous devices using, for example, pointers having grey code counters which reduce code...
5068881 Scannable register with delay test capability  
A scan-register having first and second data input ports (SYS - - DATA, SCAN - - IN), a data output port, and inputs for at least first, second, third, and fourth control signals (SYS - - CLK, M -...
5046051 Serial memory with address counter which can be preset using a multi-purpose input, and picture memory apparatus using same  
A serial memory in which serial address input devices share a terminal with control signal input devices is suitable for the non-shifting storage of information and includes at least one address...
5042007 Apparatus for transposing digital data  
A digital storage device is provided that includes a storage unit having a plurality of word storage locations, each of the word storage locations being coupled to a corresponding read enable line...
RE33664 Data shifting and rotating apparatus  
A circuit for rotating a multibit binary word in either the right or the left direction includes a scale factor decoder receiving a scale factor word which specifies the magnitude of the rotation...
5036489 Compact expandable folded first-in-first-out queue  
An expandable first-in-first-out FIFO circuit is provided for storing data words in a plurality of data cells in response to a digital position control signal generated by a plurality of control...
5027330 FIFO memory arrangement including a memory location fill indication  
A first-in, first-out, memory has a random access memory (RAM) for storing a plurality of information words seriatim. The use of such memory is significantly enhanced by arranging the memory so...
5027326 Self-timed sequential access multiport memory  
A RAM-based FIFO which provides self-timing of the data outputs in read mode. When the data output is not valid, the data output drivers are in a high-impedance condition. Therefore, FIFOs using...
5027318 Bit place oriented data storage system for digital data  
For economy in electronic components and their interconnections a multiplex memory system for temporary storage of digital signals, especially digital video signals, is made up of memory units each...
4995005 Memory device which can function as two separate memories or a single memory  
A FIFO memory device facilitates transfer of data between a host CPU and a peripheral device in one of a number of modes. In one mode, the FIFO memory device functions as two FIFO memories, one for...
4992973 Data transmission apparatus with loopback topology  
A data transmission apparatus which is connected with a shift register of a plural stages forming a forward path of data transmission line, and a shift register of a plural stages forming a...
4985867 Semiconductor memory circuit  
There is provided a semiconductor memory circuit, which is capable of changing the number of bits per word thereof and of switching between a RAM function and a FIFO function, by an external...
4962483 Cascading FIFO memory devices for sequential storing  
A FIFO memory device facilitates transfer of data between a host CPU and a peripheral device in one of a number of modes. In one mode, the FIFO memory device functions as two FIFO memories, one for...
4958377 Character string identification device with a memory comprising selectively accessible memory areas  
In a character identification device for identifying an input character to produce an identified code, a memory circuit (40) decides a match between the input character and stored characters...
4954988 Memory device wherein a shadow register corresponds to each memory cell  
A data storage device includes two registers associated with each cell of the memory. The first register forms a read/write memory register, and the second register forms a write-only shadow...
Matches 51 - 100 out of 247 < 1 2 3 4 5 >