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7609575 Method, apparatus and system for N-dimensional sparse memory using serial optical memory  
In some embodiments, a method, apparatus and system for n-dimensional sparse memory using serial optical memory are presented. In this regard, a memory device is introduced to circulate a signal...
7609574 Method, apparatus and system for global shared memory using serial optical memory  
In some embodiments, a method, apparatus and system for global shared memory using serial optical memory are presented. In this regard, a memory device is introduced to circulate a signal among a...
7489736 Block modulation  
A device and method for block transmission include a storage configured to store at least one transmission matrix relating to a set of symbols, and a processor configured to process at least part...
6947301 Content addressable memory (CAM) device employing a recirculating shift register for data storage  
A content addressable memory (CAM) device is described including a plurality of storage locations, each arranged as a recirculating shift register, and plurality of bit comparators each coupled to...
6138227 Device for the jump-like addressing of specific lines of a serially operating digital memory  
A digital memory matrix having memory cells in rows and columns, addressing of the memory cells is accomplished by control devices which perform arbitrary jumps of address, thereby avoiding...
6026027 Flash memory system having memory cache  
The present invention discloses an electronic memory system having semipermanent memory storage, a memory device for rapid data transfer and temporary memory storage, and controller for monitoring...
5801981 Serial access memory with reduced loop-line delay  
According to one aspect of the invention, a serial access memory has multiple shift registers that are clocked simultaneously for designating column addresses. Each shift register shifts an...
5732011 Digital system having high speed buffering  
A FIFO memory eliminates the delay associated with selecting memory locations during a read and write operation and prevents data intended to be saved from changing during the write operation. The...
5680341 Pipelined record and playback for analog non-volatile memory  
A non-volatile analog memory contains multiple recording pipelines for sampling and storing values representing an analog signal and/or multiple playback pipelines for playing a recorded signal....
5617368 Semiconductor memory device equipped with serial data reading circuit and method of outputting serial data from semiconductor memory  
A semiconductor memory device for serially outputting previously loaded data from an integral memory is disclosed herein. The device is configured to output head data from a predetermined location...
5598364 All-MOS precision differential delay line with delay a programmable fraction of a master clock period  
A write precompensation circuit includes a plurality of current-controlled delay buffers connected to form a delay line having selectable output taps. The precise delay of each delay buffer is...
5537552 Apparatus for selectively comparing pointers to detect full or empty status of a circular buffer area in an input/output (I/O) buffer  
An information reproducing apparatus for reproducing recorded data includes a buffer, a control device and a determining device. The buffer stores data blocks read out from a recording medium and...
5485597 A CCD array memory device achieving high speed accessing by writing and reading data through a cache memory  
A memory device for storing analog or multilevel data which is easy to produce and of a small scale. The memory device according to the present invention circulates data between a plurality of...
5473756 FIFO buffer with full/empty detection by comparing respective registers in read and write circular shift registers  
A method and apparatus for generating control signals for a high speed First In First Out (FIFO) buffer. Moreover, the present invention limits the instances where signal glitches may occur. A...
5469398 Selectable width, brustable FIFO  
A selectable width, burstable FIFO is described. A register memory stores x-bit and y-bit data. Each register of the register memory is y+1 bits wide. Y bits store x-bit and y-bit data and 1-bit...
5388238 System and method for monitoring the validity of circulating pointers in a FIFO memory  
A system and method are described for enforcing the validity of circulating pointers stored in a pointer FIFO (first-in-first-out) memory. One or more target pointers are generated and compared to...
5305253 Zero fall-through time asynchronous fifo buffer with nonambiguous empty-full resolution  
A First In First Out shift register memory system (10) with a plurality of memory word registers (50) having data inputs connected to a common data-in bus (16), and a plurality of data outputs...
5270981 Field memory device functioning as a variable stage shift register with gated feedback from its output to its input  
A memory device having an addressing unit for addressing different values as addresses for input/output of data for each clock input during one cycle, and a memory inputting data at different...
5204833 Method and apparatus for recording waveform  
There is provided method and apparatus for recording a waveform. By counting the intervals of change points of a recorded waveform and recording the count data, the waveform can be recorded for a...
5193153 System for detecting overwriting of data in a buffer memory, particularly for a data switch  
Information concerning the access to a first-in first-out buffer memory for reading and writing operations is indicated by the use of two supplemental memories which provide availability and...
5117388 Serial input/output semiconductor memory  
A semiconductor memory comprises a memory cell array which includes a plurality of memory cells respectively connected to one of a plurality of word lines and to one of a plurality of bit lines, a...
5109358 Optical flip-flop circuit  
An optical flip-flop circuit which includes an electrical power source for providing an electrical signal, a light-receiving element provided in series with the power source for switching the...
5084839 Variable length shift register  
Forming the shift register as a plurality of memory locations in a memory array where the input port for writing into the memory and the output port for reading out of the memory are sequenced...
5068881 Scannable register with delay test capability  
A scan-register having first and second data input ports (SYS - - DATA, SCAN - - IN), a data output port, and inputs for at least first, second, third, and fourth control signals (SYS - - CLK, M -...
5058060 Optical memory cell  
An optical memory cell constructed from an optical combiner, a 1×2 optical swtich and optical fibers. One input port of the optical combiner serves as the input to the memory cell. The output port...
5036489 Compact expandable folded first-in-first-out queue  
An expandable first-in-first-out FIFO circuit is provided for storing data words in a plurality of data cells in response to a digital position control signal generated by a plurality of control...
4922457 Serial access memory system provided with improved cascade buffer circuit  
A serial access memory device with the improved cascade buffer circuit for controlling serial access operation which has a small number of external terminals is disclosed. The cascade buffer...
4901286 Digital FIFO memory  
A digital FIFO memory is disclosed which is formed by a memory cell array (zf) comprising of n signal channels (b1 . . . bn) each containing m memory cells (c..1, c..2, c..m-1, c..m) are first,...
4890261 Variable word length circuit of semiconductor memory  
A word length variable circuit of a semiconductor memory comprises a shift register provided corresponding to rows or columns of a memory cell array. The input of the first stage of the shift...
4873663 Control memory using recirculating shift registers for a TDM switching apparatus  
A memory matrix for storing control words for controlling a common control time division multiplexed (TDM) switch is formed by employing a plurality of shift registers connected in recirculating...
4833655 FIFO memory with decreased fall-through delay  
A first-in, first out data memory minimizes fall-through delay. The FIFO memory has a plurality of cascaded register stages arranged in sections, with the input of each section selectively coupled...
4825409 NMOS data storage cell for clocked shift register applications  
An improved NMOS storage cell for use in shift registers is disclosed. Among other components, it contains a pair of inverters--one them an enabling inverter. A pre-charge transistor is placed in...
4815804 In-line fiber optic memory and method of using same  
A fiber optic recirculating memory comprises a splice-free length of optical fiber which forms a loop that is optically closed by means of a fiber optic coupler. The coupler couples an optical...
4800534 Integrated memory circuit  
An integrated memory circuit includes a memory loop which comprises two gates which are controlled by a clock signal. The circuit is susceptible to a race condition so that correct operation cannot...
4779233 Control of read-out from a RAM  
A circuit arrangement for controlling the read-out of stored information composed of first and second random access memories each having a plurality of addressable memory locations having a...
4706217 Sequential logic circuit  
A circuit has a logic memory, a preceding logic circuit, a succeeding logic circuit, and a function defining circuit. An input signal is taken by the preceding logic circuit, where a new logic...
4656666 Method and apparatus for handling information  
A continuously-flowing loop of electromagnetic energy extends between Earth and an object in space. Information is both loaded into the loop and extracted therefrom. To these ends, a first...
4539657 Memory system  
Apparatus for storing a periodic signal and for recycling complete cycle portions of such stored periodic signal is provided, such apparatus comprising: means for converting an input sinusoidal...
4506348 Variable digital delay circuit  
A variable digital delay circuit is disclosed which utilizes a shift register to periodically sample a signal to be delayed and after a predetermined number of samples are collected as a group of...
4481608 Reentrant asynchronous FIFO  
Cyclic instrument control and data acquisition functions which are critically dependent upon synchrony are directed from a computer based system including a FIFO buffer adapted to feedback the most...
4471469 Negative resistance bubble memory and display device  
Disclosed is a memory or display device which includes a shift register having a bubble generator, a bubble propagator, and a bubble annihilator. Front and back glass plates are provided with...
4428070 Dynamic circulation memory  
A dynamic circulation memory is provided comprising a charge transfer device with surplus-value storage and an adaptive refreshing circuit for maximum information storage. Reference-charge packets...
4415991 Multiplexed MOS multiaccess memory system  
Multiaccess memory modules are each connected by means of a bus to a system ddress multiplexer and to a system data multiplexer/demultiplexer. Each module includes a multiaccess memory connected to...
4390970 Rotating register utilizing field effect transistors  
A storage register which may be used to store several sets of data. The storage register may also be used as a demultiplexer to separate two or more sets of data that were received by the register...
4386421 Memory device  
A memory device having a large memory capacity which can be utilized either as a random access memory or a serial access memory is disclosed. The memory device comprises memory cells arrayed in a...
4365318 Two speed recirculating memory system using partially good components  
A CCD recirculating memory system is disclosed in which "partially good" CCD memory chips and "all good" memory chips are mounted on memory cards. The defective portions of the partially good chips...
4333161 Data processing apparatus operative on data passing along a serial, segmented store  
A serial recirculating store is provided with data processing units distributed along its length and a fast data line interacts with the serial store at each processing unit for controlling...
4332015 Remote temperature-pressure recording system  
A remote recording and playback system comprises a recording unit for recording analog data received virtually simultaneously over a plurality of analog input channels, and a playback unit for...
4313159 Data storage and access apparatus  
Data storage and access apparatus for multi-dimensional data processing. The apparatus includes a storage shift register array (SSRA) to permit data storage and one or more storage/access shift...
4305138 Stack memory device  
A stack memory device which comprises a memory stack of n-bit registers with gating circuiting controlled by code inverters to allow first in - first out, first in - last out, last in - first out...
Matches 1 - 50 out of 141 1 2 3 >