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7630233 |
Semiconductor device and driving method of the same
The invention provides a semiconductor device including a memory of a simple structure to provide an inexpensive semiconductor device and a driving method thereof. The semiconductor device of the...
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7630224 |
Semiconductor integrated circuit device and layout method thereof
A semiconductor integrated circuit device includes a memory macro and M (M is an integer more than 1) passage wirings. The memory macro includes a memory cell array comprising memory cells which...
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7630223 |
Memory device and method of arranging signal and power lines
A memory device and method for arranging signal and power lines includes a plurality of sub-memory cell arrays having a plurality of memory cells, a plurality of sense amplifiers to sense and...
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7623398 |
Semiconductor memory device and semiconductor device
Disclosed is a module where semiconductor memory devices each having a DLL (Delay Lock Loop) are stacked or a multi-chip module (MCM) having the semiconductor memory devices, a dedicated pad for...
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7623397 |
Semiconductor device
A semiconductor device with a packaging circuit portion connected to a semiconductor chip therein. The semiconductor chip includes a plurality of pad electrodes, and the packaging circuit portion...
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7623366 |
Semiconductor device having a field effect source/drain region
A semiconductor device includes an active region defined in a semiconductor substrate, and gate electrodes crossing over the active region. Source/drain regions are defined in the active region on...
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7623365 |
Memory device interface methods, apparatus, and systems
Apparatus and systems may include a substrate, an interface chip disposed on the substrate, a first memory die having a plurality of memory arrays disposed on the interface chip, the first memory...
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7623364 |
Semiconductor device
A technology that makes it possible to reduce fluctuation in operating voltage for operating the circuits formed in the core region of a semiconductor device is provided. This semiconductor device...
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7619945 |
Memory power management
Memory power management is described. A non-volatile memory array is provided, the array including separately controlled memory blocks. At least two charge pumps are coupled to the array, the...
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7619916 |
8-T SRAM cell circuit, system and method for low leakage current
An SRAM cell has reduced gate and sub-threshold leakage currents. The SRAM cell is designed to include eight operatively coupled transistors to reduce leakage currents irrespective of data stored...
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7619913 |
Device, method and program for managing area information
In an apparatus for managing area data, the first data structure for area management includes: a first index data structure including a first root node corresponding to a first set of areas...
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7616630 |
Semiconductor memory device
A semiconductor memory device resolves skew problem due to delay difference between the case when data that is inputted through data input/output (IO) pin is transferred to one global I/O bus and...
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7616489 |
Memory array segmentation and methods
The invention provides methods and apparatus. A memory array has a first well region having a first conductivity type. A plurality of second well regions of a second conductivity type is formed in...
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7614027 |
Methods for forming a MRAM with non-orthogonal wiring
The present subject matter allows non-orthogonal lines to be formed at the same thickness as the orthogonal lines so as to promote compact designs, to be formed with even line edges, and to be...
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7613026 |
Apparatus and methods for optically-coupled memory systems
Optically-coupled memory systems are disclosed. In one embodiment, a system memory includes a carrier substrate, and a controller attached to the carrier substrate and operable to transmit and...
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7613025 |
Dram cell design with folded digitline architecture and angled active areas
The present invention is generally directed to a DRAM cell design with folded digitline sense amplifier. In one illustrative embodiment, a memory array having a plurality of memory cells having an...
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7613024 |
Local digit line architecture and method for memory devices having multi-bit or low capacitance memory cells
A DRAM array includes for each column a pair of complimentary digit lines that are coupled to a sense amplifier. Each of the global digit lines is selectively coupled to a plurality of local digit...
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7613023 |
Memory arrangement, particularly for the non-volatile storage of uncompressed video and/or audio data
When recording uncompressed video and/or audio data using a digital video recorder, there is the need for a robust memory arrangement based on non-volatile, integrated circuits which is able to be...
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7613022 |
Semiconductor memory device and method of forming the same
Example embodiments provide a semiconductor memory device and method of forming a semiconductor memory device that may equalize load due to a coupling capacitance between a line and a component...
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7610447 |
Upgradable memory system with reconfigurable interconnect
Described herein is a point-to-point memory communications architecture, having a point-to-point signal line set associated with each of a plurality of connectors or module positions. When the...
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7609550 |
Compact virtual ground diffusion programmable ROM array architecture, system and method
A compact, shared source line and bit line architecture for a diffusion programmable ROM. In one embodiment, a ROM circuit or instance includes a plurality of storage cells organized as an array of...
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7609538 |
Logic process DRAM
A semiconductor integrated circuit device includes a dynamic random access memory (DRAM) unit. The DRAM unit comprises a plurality of bit line pairs. Each bit line pair includes a first bit line...
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7606061 |
SRAM device with a power saving module controlled by word line signals
An SRAM device include: a latch unit for retaining data; one or more pass gate transistors controlled by a word line for coupling the latch unit to a bit line and a complementary bit line; and a...
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7606057 |
Metal line layout in a memory cell
A memory cell includes polysilicon gates 2 running in a first direction. A sequence of layers metal lines includes a layer of bit lines 4 running in a second direction substantially orthogonal...
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7606056 |
Process for manufacturing a phase change memory array in Cu-damascene technology and phase change memory array thereby manufactured
A process for manufacturing a phase change memory array includes the steps of: forming a plurality of phase change memory cells in an array region of a semiconductor wafer, the phase change memory...
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7606055 |
Memory architecture and cell design employing two access transistors
An improved memory array architecture and cell design is disclosed in which the cell employs two access transistors. In one embodiment, the two access transistors in each cell are coupled at one of...
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7603510 |
Semiconductor device and storage cell having multiple latch circuits
A semiconductor storage device including a first latch circuit for latching stored data and a storage cell part including a plurality of second latch circuits that operate with inverted logic from...
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7602665 |
Semiconductor integrated circuit device
A clock-generating circuit for forming internal clock signals by comparing a signal obtained by delaying, through a variable delay circuit, an input clock signal input through an external terminal...
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7602634 |
Dynamic RAM storage techniques
Dynamic RAM (DRAM) cells are provided. Data can be read from a DRAM cell without draining the stored charge stored in the cell. During a read cycle, current flows between a Read Bit line and a...
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7602630 |
Configurable inputs and outputs for memory stacking system and method
Embodiments of the present invention relate to configurable inputs and/or outputs for memory and memory stacking applications. More specifically, embodiments of the present invention include memory...
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7599239 |
Methods and systems for reducing heat flux in memory systems
Systems and methods for reducing heat flux in memory systems are described. In various embodiments, heat flux reductions are achieved by manipulating the device IDs of individual memory devices...
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7599217 |
Memory cell device and manufacturing method
A memory cell device, having a memory material switchable between electrical property states by the application of energy, comprises an electrode, a separation layer against an electrode surface, a...
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7599205 |
Methods and apparatus of stacking DRAMs
Large capacity memory systems are constructed using stacked memory integrated circuits or chips. The stacked memory chips are constructed in such a way that eliminates problems such as signal...
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7599167 |
Active balancing circuit modules, systems and capacitor devices
Circuit modules, systems and devices for controlling voltages across capacitors.
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7596011 |
Logic process DRAM
An integrated circuit device comprises a plurality of bit line pairs. First and second bit lines are aligned with each other in an end-to-end arrangement. The first and second bit lines are...
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7593284 |
Memory emulation using resistivity-sensitive memory
Interface circuitry in communication with at least one non-volatile resistivity-sensitive memory is disclosed. The memory includes a plurality of non-volatile memory elements that may have...
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7593282 |
Memory core with single contacts and semiconductor memory device having the same
A memory core includes a first sub-memory array including a plurality of first memory cells, a second sub-memory array including a plurality of second memory cells, a bit line amplification circuit...
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7586786 |
Nonvolatile semiconductor memory
A method of reading out data from nonvolatile semiconductor memory including the steps of applying a first voltage to a bit line contact; applying a second voltage to a source line contact, wherein...
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7583524 |
Nonvolatile semiconductor memory device
A nonvolatile semiconductor memory device includes a plurality of 3-dimensional cell arrays to reduce the chip size. The nonvolatile semiconductor memory device includes a unit block cell array...
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7580316 |
Semiconductor memory device
Subarrays, which constitute a memory cell array, each include a bit line driving transistor having a drain connected to a bit line, a source is connected to an interconnection having a power supply...
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7580304 |
Multiple bus charge sharing
A charge-sharing circuit includes a first input bus pair, a second input bus pair, and an output bus pair. A capacitor is coupled between a first internal node and a second internal node. A first...
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7580273 |
Digital memory with controllable input/output terminals
Methods and apparatus for controlling an input/output (I/O) driver of an I/O terminal based at least in part on the values being provided to the I/O terminal is disclosed. In various embodiments, a...
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7577789 |
Upgradable memory system with reconfigurable interconnect
Described are systems that employ configurable on-die termination elements that allow users to select from two or more termination topologies. One topology is programmable to support rail-to-rail...
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7577760 |
Memory systems, modules, controllers and methods using dedicated data and control busses
A memory system includes a plurality of memory devices arranged in sets on at least one memory module, each set including at least one memory device. In some embodiments, the system further...
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7577041 |
Semiconductor memory device and writing method thereof
A semiconductor memory device includes a power supply circuit which generates a write current, a write line to which a logic state is transferred, a first pass transistor connected between the...
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7577010 |
Integrated circuits, methods for manufacturing integrated circuits, integrated memory arrays
The present invention relates generally to integrated circuits, to methods for manufacturing integrated circuits, and to integrated memory arrays.
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7573775 |
Setting threshold voltages of cells in a memory block to reduce leakage in the memory block
In one embodiment, a memory block includes one or more bit lines that each include two or more cells. Each cell in each bit line has a distance from a sense amplifier coupled to the bit line, and...
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7573745 |
Multiple use memory chip
A die for a memory array may store Flash and EEPROM bits in at least one Nitride Read Only Memory (NROM) array. Each array may store Flash, EEPROM or both types of bits.
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7573733 |
Self-identifying stacked die semiconductor components
A semiconductor die having a functional circuit (e.g., a memory array) and a decode circuit suitable for use in a stacked die semiconductor component (e.g., a random access memory component) is...
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7570509 |
Semiconductor device, logic circuit and electronic equipment
A semiconductor device comprises: a) a multiple layered substrate including a semiconductor substrate, an insulation film formed on the semiconductor substrate, and a semiconductor film, b) a first...
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