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9042149 Volatile memory access via shared bitlines  
A memory includes an array of memory cells that form rows and columns. The rows of the array include memory cell pairs. The memory cells may include two cross-coupled inverters and two...
9036406 Magneto-resistive memory device including source line voltage generator  
A MRAM includes a memory cell array of spin-transfer torque magnetic random access memory (STT-MRAM) cells and a source line commonly connected to the plurality of STT-MRAM cells. A source line...
9036437 Method and apparatus for testing memory utilizing a maximum width of a strobe signal and a data width of a data signal  
A method and an apparatus for testing a memory are provided, and the method is adapted for an electronic apparatus to test the memory. In the method, a left edge and a right edge of a first...
9036402 Arrays of vertically stacked tiers of non-volatile cross point memory cells  
An array of vertically stacked tiers of non-volatile cross point memory cells includes a plurality of horizontally oriented word lines within individual tiers of memory cells. A plurality of...
9030858 Semiconductor device and structure  
A semiconductor device, including: a first semiconductor layer including first transistors, wherein the first transistors are interconnected by at least one metal layer including aluminum or...
9030865 Circuit arrangement and method of forming the same  
In various embodiments, a circuit arrangement may be provided including a data cell. The circuit arrangement may further include a first transistor and a second transistor. The first controlled...
9029956 SRAM cell with individual electrical device threshold control  
A static random access memory cell is provided that includes first and second inverters formed on a substrate each having a pull-up and pull-down transistor configured to form a cell node. Each of...
9030859 Three dimensional non-volatile storage with dual layers of select devices  
A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are...
9025355 Non-volatile memory device with clustered memory cells  
An embodiment of a non-volatile memory device includes: a memory array, having a plurality of non-volatile logic memory cells arranged in at least one logic row, the logic row including a first...
9025377 Method of operating semiconductor memory device  
According to one embodiment, a method of operating a semiconductor memory device is disclosed. The method can include storing read-only data in at least one selected from a memory cell of an...
9019739 Three-dimensional semiconductor devices and methods of fabricating the same  
According to example embodiments of inventive concepts, a three-dimensional semiconductor device may include: a memory cell array including memory cells that may be arranged three-dimensionally,...
9019738 Memory device having sequentially cascading dices  
A memory device is provided. The memory device is used for data transmission at around 1600 megahertz (MHz). A wire layout is used to sequentially cascade memory dices with greatly shortened...
9019768 Split page 3D memory array  
A semiconductor device includes active strips. Active strip stack selection structures electrically couple to the active strip stacks at positions between the first and second ends, and select...
9007812 Memory device comprising a cell array overlapping a driver circuit  
An object of one embodiment of the present invention is to propose a memory device in which a period in which data is held is ensured and memory capacity per unit area can be increased. In the...
9007806 Electromechanical integrated memory element and electronic memory comprising the same  
An electromechanical memory element includes a fixed body and a deformable element attached to the fixed body. An actuator causes a deformation of the deformable element from a first position...
9007865 Memory circuit, persistent after the removal of the power supply  
According to some embodiments, an electronic circuit comprises a digital output which is held to a logic one after the power supply was removed, for a time duration in a narrow range. The...
9007803 Integrated circuits with programmable electrical connections and methods for fabricating the same  
Methods and apparatus are provided for an integrated circuit with a programmable electrical connection. The apparatus includes an inactive area with a memory line passing over the inactive area....
9001562 Semiconductor memory device including a dummy block  
A semiconductor memory device includes a memory array including a plurality of element blocks; the plurality of element blocks including end-portion element blocks arranged at an end portion of...
9001548 Memory device interface methods, apparatus, and systems  
Apparatus and systems for memory system are provided. In an example, an interface chip can include a memory controller configured to couple to a processor and to couple to a plurality of stacked...
9001546 3D structure for advanced SRAM design to avoid half-selected issue  
Disclosed is a novel static random access memory (SRAM) device. The SRAM device comprises a plurality of memory array layers vertically disposed one above another, a layer decoder circuit disposed...
9001565 Semiconductor device with memory device  
A memory mat (101) includes a main body portion (200) that includes a first capacitor (203A), a linear conductive film (204) that is formed between the main body portion (200) and a peripheral...
9001580 Asymmetric dense floating gate nonvolatile memory with decoupled capacitor  
A nonvolatile memory (“NVM”) bitcell includes a capacitor, an asymmetrically doped transistor, and a gated diode device. The capacitor, transistor, and gated diode device are each electrically...
9001605 Method of overlapping interconnect signal lines for reducing capacitive coupling effects  
Described herein are various principles for designing, manufacturing, and operating integrated circuits having functional components and one or more metal interconnect layers, where the dimensions...
8995161 Apparatus and methods to perform read-while write (RWW) operations  
Subject matter disclosed herein relates to methods and apparatus, such as memory devices and systems including such memory devices. In one apparatus example, a plurality of block configurations...
8995160 Electronic component including a matrix of TCAM cells  
Electronic component including a ternary content-addressable memory component, configured to compare the input data items with a set of pre-recorded reference data words; the memory component...
8988919 Semiconductor device having a control chip stacked with a controlled chip  
A semiconductor device includes a first controlled chip and a control chip stacked therewith. The first controlled chip includes a first circuit outputting a data signal in response to a...
8988917 Bit line resistance compensation  
Methods for compensating for variations in bit line resistance in non-volatile memories are described. In some embodiments, use of multiple patterning lithography for forming bit lines may lead to...
8988931 Permutational memory cells  
Various embodiments comprise apparatuses having at least two resistance change memory (RCM) cells. In one embodiment, an apparatus includes at least two electrical contacts coupled to each of the...
8982599 Chip die and semiconductor memory device including the same  
A chip die including a first input/output (I/O) pad configured to transmit/receive an I/O signal of a memory cell array included in the chip die; a second I/O pad configured to, if a stacked chip...
8982660 Semiconductor memory device and method for word line decoding and routing  
The invention discloses a semiconductor memory device and a method for word line decoding and routing. The present invention relates generally to semiconductor memory field, Problems solved by the...
8982597 Memory system with sectional data lines  
The system includes multiple sets of local data lines in one or more routing metal layers below the three-dimensional memory array and multiple sets of global data lines in one or more top metal...
8982598 Stacked memory device with redundant resources to correct defects  
A memory device includes a stack of circuit layers, each circuit layer having formed thereon a memory circuit configured to store data and a redundant resources circuit configured to provide...
8976562 Resistive memory architectures with multiple memory cells per access device  
A resistive memory structure, for example, phase change memory structure, includes one access device and two or more resistive memory cells. Each memory cell is coupled to a rectifying device to...
8976576 Static random access memory structures  
A static random access memory structure is provided. The static random access memory structure includes a storage region having a first storage node and a second storage node which is...
8971085 Self-refresh adjustment in memory devices configured for stacked arrangements  
Disclosed are various embodiments related to stacked memory devices, such as DRAMs, SRAMs, EEPROMs, and CAMs. For example, stack position identifiers (SPIDs) are assigned or otherwise determined,...
8971084 Context protection for a column interleaved memory  
A semiconductor memory cell includes a set of circuit structures, each having column input/output circuits. The semiconductor memory cell further includes a set of replicas corresponding to the...
8964453 SRAM layouts  
Roughly described, the cell layout in an SRAM array is re-arranged such that the gate electrodes for transistors for which flexibility to use one channel length is desired, are formed along a...
8964439 Semiconductor device having hierarchical bit line structure  
A semiconductor device comprises first and second global bit lines, a sense amplifier amplifying a voltage difference of the first and second global bit lines, first and second local bit lines...
8964443 Method for improving bandwidth in stacked memory devices  
Apparatus and methods of increasing the data rate and bandwidth of system memory including stacked memory device dice. The system memory includes a memory device having a plurality of memory...
8964454 Three-dimensional static random access memory cell  
Systems and methods are provided for fabricating a static random access memory (SRAM) cell in a multi-layer semiconductor device structure. The SRAM cell includes two pull-up transistors, two...
8964440 Stacked semiconductor devices including a master device  
A stack that includes non-volatile memory devices is disclosed. One of the non-volatile memory devices in the stack is a master device, and the remaining memory device or devices is a slave device(s).
8963115 Memory device and method of manufacturing memory device  
According to one embodiment, a memory device includes a first conductive line extending in a first direction, second conductive lines each extending in a second direction intersect with the first...
8964441 Semiconductor memory device  
A semiconductor memory device includes a plurality of first regions formed in a line-type and extending in a first direction, and a plurality of second regions and a plurality of third regions...
8964494 memories and methods for repair in open digit memory architectures  
A memory with extra digit lines in full size end arrays with an open digit architecture, which can use the extra digit lines to form repair cells. In one example, folded digit sense amplifiers are...
8958228 Non-volatile memory having 3D array of read/write elements with vertical bit lines and select devices and methods thereof  
A three-dimensional memory is formed as an array of memory elements that are formed across multiple layers of planes positioned at different distances above a semiconductor substrate. The memory...
8958227 Accessing or interconnecting integrated circuits  
Multiple integrated circuits (ICs) die, from different wafers, can be picked-and-placed, front-side planarized using a vacuum applied to a planarizing disk, and attached to each other or a...
8953394 Semiconductor device capable of operating in both a wide input/output mode and a high-bandwidth mode  
A logic chip and memory chip stacked over the logic chip, the logic chip having a first surface facing the memory chip and a second surface opposite to the first surface and including: first and...
8953396 NAND interface  
A NAND interface having a reduced pin count configuration, in which all command and address functions and operations of the NAND are provided serially on a single serial command and address pin,...
8953402 Semiconductor memory with sense amplifier  
In an exemplary aspect, the present invention provides a semiconductor memory device including sense amplifiers that drive bit lines to which memory cells are connected, and driver transistors...
8947908 Hetero-switching layer in a RRAM device and method  
A non-volatile memory device structure includes first electrodes comprising conductive silicon-containing material, a plurality of resistive switching material stacks comprising first resistive...