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7633784 Junction field effect dynamic random access memory cell and content addressable memory cell  
A semiconductor memory device including a dynamic random access memory (DRAM) cell and a ternary content addressable memory (TCAM) cell is disclosed. The DRAM cell may include a data storing...
7602629 Content addressable memory  
Systems, devices, and methods, including executable instructions are provided for content addressable memory (CAM). One method includes writing entries, including a type field, to a ternary content...
7598544 Hybrid carbon nanotude FET(CNFET)-FET static RAM (SRAM) and method of making same  
Hybrid carbon nanotube FET (CNFET), static ram (SRAM) and method of making same. A static ram memory cell has two cross-coupled semiconductor-type field effect transistors (FETs) and two nanotube...
7587532 Full/selector output from one of plural flag generation count outputs  
A method and apparatus for adaptive buffer sizing adjusts the size of the buffer at different levels using a “high water mark” to different levels for different system conditions. The high...
7558095 Memory cell for content-addressable memory  
A memory cell for use in a content-addressable memory comprises a first latch and a second latch. The first latch is operative to store a first bit associated with a first stored word, while the...
7548456 Combo memory cell  
A combo memory cell having a SRAM cell and a mask-ROM code programmer. The SRAM cell comprises first and second inverters. The first inverter comprises a first PMOS transistor and a first NMOS...
7542329 Virtual power rails for integrated circuits  
Methods and apparatuses to decrease power consumption and reduce leakage current of integrated circuits are disclosed. New leakage power saving techniques for various types of integrated circuits,...
7535752 Semiconductor static random access memory device  
According to an aspect of the invention there is provided a semiconductor memory device, including a first inverter being composed of a first P-channel MOS transistor, a first N-channel MOS...
7499303 Binary and ternary non-volatile CAM  
A CAM cell array according to embodiments of the present invention include an array of CAM cells, each of the CAM cells comprising a first cell, the first cell including a non-volatile storage...
7423895 High-speed and low-power differential non-volatile content addressable memory cell and array  
A differential non-volatile content addressable memory array has a differential non-volatile content addressable memory cell which uses a pair of non-volatile storage elements. Each of the...
7414873 Low-power CAM cell  
A CAM cell is provided that includes: an SRAM cell adapted to store a bit; a data line adapted to provide a corresponding comparand bit; an XOR gate adapted to XOR the stored bit and the comparand...
7400520 Low-power CAM  
In one embodiment, a CAM is provided that includes; a plurality of memory cells grouped to store a word, wherein the memory cells are organized into a plurality of ripple groups, each ripple group...
7391633 Accelerated searching for content-addressable memory  
A sensing circuit for use with a CAM circuit including multiple match lines and multiple CAM cells connected to the match lines includes at least one charge sharing circuit and at least one...
7280378 CAM cells and CAM matrix made up of a network of such memory cells  
A content addressable memory (CAM) includes first and second memory circuits and a comparison circuit. The first memory circuit includes first and second sets of transistors for the storage of...
7277309 Interlocking memory/logic cell layout and method of manufacture  
A memory/logic cell layout structure includes a pair of memory/logic cells formed on a substrate. Each memory/logic cell ( 102, 104 ) can include a pair of memory areas to store data ( 106 - 0/106...
7236408 Electronic circuit having variable biasing  
Techniques are provided for selectively biasing wells in a circuit, such as a Complementary Metal Oxide Semiconductor (CMOS) circuit, that has two types of transistors, one type formed on a...
7221575 Pseudo ternary content addressable memory device having row redundancy and method therefor  
A pseudo ternary content addressable memory (PTCAM) device ( 100 ) can include a number of PTCAM blocks ( 102 - 0 to 102 - 63 ), each of which can include a number of standard PTCAM rows ( 106 -...
7193905 RRAM flipflop rcell memory generator  
An RRAM flip-flop rcell memory of the type having a write address decoder, a read address decoder, a set of n flip flops, one AND gate associated with each flip flop in the set, a set of w OR gates...
7151521 Methods and apparatus for driving pixels in a microdisplay  
A pixel is driven with pulse width modulation (PWM). A cycle for the PWM signal is divided into a plurality of super-intervals. Each of the super-intervals is divided into a plurality of intervals....
7151682 Method and apparatus to read information from a content addressable memory (CAM) cell  
A method and apparatus to read information from a content addressable memory (CAM) cell of a nonvolatile memory is provided. The apparatus may be a nonvolatile memory that may include a first...
7126834 Sense amplifier architecture for content addressable memory device  
A content addressable memory (CAM) device ( 200 ) can equalize a potential between a match line ( 202 ) and corresponding pseudo-supply (PVSS) line ( 204 ) in a pre-sense operation. In a sense...
7120040 Ternary CAM cell for reduced matchline capacitance  
A ternary content addressable memory (CAM) cell is disclosed for providing reduced or minimized matchline (ML) capacitance and for increasing current between matchline and tail-line in the case of...
7110275 High speed NAND-type content addressable memory (CAM)  
A CAM block includes a CAM array having a plurality of rows and columns of 4-bit NAND-type CAM cells therein. Each of a plurality of the NAND-type cells includes a respective ladder-type compare...
7102904 System and method for minimizing noise on a dynamic node  
A circuit for comparing a first match line and a second match line in a CAM circuit. The circuit includes a first keeper circuit having a first input coupled to the second match line and a second...
7099171 Content addressable memory cell techniques  
A content addressable memory cell ( 10 ) includes a circuit ( 20 ) operating from a predetermined supply voltage (VDD) for storing a first bit of data at a first point ( 35 ) and a second bit of...
7095640 Multiple match detection circuit and method  
A multiple matchline sense circuit for detecting a single, more than one, or no match conditions during a search-and-compare operation of a content addressable memory is disclosed. The circuit...
7068545 Data processing apparatus having memory protection unit  
A data processor ( 100 ) has a memory operable to store data values; a memory protection unit ( 130 ) operable to associate memory attributes with portions of said memory and to identify a...
6995997 Cache cell with masking  
A CAM cell with masking made in the form of an integrated circuit, including a first storage cell including a first transistor, first and second inverters in anti-parallel, and a second transistor;...
6982891 Re-configurable content addressable/dual port memory  
A re-configurable core cell is provided that can be used as either a content addressable memory cell or a dual-ported static read only memory cell. The re-configurable core cells are pre-diffused...
6970368 CAM (content addressable memory) cells as part of core array in flash memory device  
In a method and system for providing a CAM (content addressable memory) cell of a flash memory device, a respective core flash memory cell to be used as the CAM cell is fabricated as part of a core...
6967857 Dense content addressable memory cell  
A content addressable memory cell ( 10 ) comprises a word line 12 , a first bit line ( 14 ), and a second bit line ( 16 ). A pair of transistors ( 30–31 ) is arranged to store bits of data at...
6944710 Multiple category CAM  
An apparatus and method is disclosed for a CAM match detection circuit with a multiple category CAM circuit. The multiple category CAM circuit provides category association tables to specify which...
6874058 Content addressed memories  
A content addressable memory comprises a CAM control logic unit and plural cells connected in a chain. Each cell comprises a memory block coupled to a common address bus, a comparator coupled to a...
6867990 Reducing power dissipation in a match detection circuit  
A CAM match detection circuit that maintains established levels of accuracy while greatly reducing the amount of power dissipated is disclosed. Rather than allowing the Matchline 185 voltage to...
6775167 System and method for low power searching in content addressable memories using sample search words to save power in compare lines  
An invention is provided for low power searching in a CAM using sample words to save power in the compare lines. The invention includes comparing a sample section of stored data to a corresponding...
6751111 High density memory cell  
A memory cell comprising an inverting stage, an access transistor coupled between a data line and an input of the inverting stage, the access transistor being responsive to a control signal for...
6707718 Generation of margining voltage on-chip during testing CAM portion of flash memory device  
For generating a margining voltage for biasing a gate of a CAM (content addressable memory) cell of a flash memory device fabricated on a semiconductor wafer, a high voltage source is provided with...
6577520 Content addressable memory with programmable priority weighting and low cost match detection  
A content addressable memory with programmable priority weighting and low cost match detection is described. A CAM array provides match and no-match indications of an input data word to a weight...
6370052 Method and structure of ternary CAM cell in logic process  
A ternary dynamic CAM cell compatible with a standard logic process includes two ratio-independent 4-transistor (4T) SRAM cells. Each 4T SRAM cell includes a pair of cross-coupled driver...
6266262 Enhanced binary content addressable memory for longest prefix address matching  
A modified binary content addressable memory (CAM) (700) having a fast variable prefix matching capability is disclosed. The modified CAM (700) includes modified CAM cells (702(0,0) to 702(n,m)),...
6157558 Content addressable memory cell and array architectures having low transistor counts  
An SRAM-based CAM cell and CAM array architecture reduce transistor count and memory size by replacing pass transistors and search transistors of conventional SRAM-base CAM cells with a pair of...
6101116 Six transistor content addressable memory cell  
A six transistor content addressable memory (CAM) cell that prevents disturb of non-written rows during a write operation. The CAM cell comprises an SRAM cell having a pair of cross-coupled...
5973949 Input structure for analog or digital associative memories  
An input structure for associative memories, including an array of elementary cells, a number of input lines, a number of output lines, a number of address lines, and a number of enable lines. Each...
5917743 Content-addressable memory (CAM) for a FLASH memory array  
A content addressable memory (CAM) cell for a FLASH memory array includes four multiple-row columns of FLASH cells formed in a virtual ground architecture having a single diffusion between...
5854761 Cache memory array which stores two-way set associative data  
A cache memory array stores two-way set associative data. An odd set data bank stores odd number sets of the two-way set associative data, where the two ways of each odd number set are aligned...
5854760 Two-dimensional PE array, content addressable memory, data transfer method and mathematical morphology processing method  
A two-dimensional PE (processing element) array that can achieve a small amount of hardware, short transfer time and high flexibility. It includes q×r CAMs, where q and r are any integers equal to...
5831889 Cache memory device and manufacturing method thereof  
A method is for manufacturing a cache memory device for writing cache data into and reading cache data from a storing region of a memory cell array designated according to a portion of an address...
5793663 Multiple page memory  
A memory system is able to simultaneously access multiple rows in page mode operation. The multiple page memory includes a memory array with multiple internal read registers to improve the...
5774403 PVT self aligning internal delay line and method of operation  
An integrated circuit process, voltage and temperature fluctuation self-aligning internal delay line circuit and method of operation. A PVT related reference signal is compared to a set of...
5657264 Semiconductor memory  
A semiconductor memory comprises a write driver which is provided to correspond to respective data line and by which data lines connected with a memory cell through the control of a word line are...
Matches 1 - 50 out of 109 1 2 3 >