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9042162 SRAM cells suitable for Fin field-effect transistor (FinFET) process  
A static random access memory (SRAM) cell includes first and second n-channel transistors, first and second p-channel transistors, first and second enable transistors, and first and second pass...
9043561 Storage device  
To provide a storage device with low power consumption. The storage device includes a plurality of cache lines. Each of the cache lines includes a data field which stores cache data; a tag which...
9036404 Methods and apparatus for SRAM cell structure  
An SRAM cell structure. In one embodiment, a bit cell first level contacts formed at a first and a second CVdd node, a first and a second CVss node, at a bit line node, at a bit line bar node, at...
9007799 Low power content addressable memory system  
A content addressable memory (CAM) system includes one or more CAM cells, each including a bit cell to store a bit and a complementary bit, and a compare circuit to compare a reference input to...
9007798 Nearest neighbor serial content addressable memory  
A digital design and technique may be used to implement a Manhattan Nearest Neighbor content addressable memory function by augmenting a serial content addressable memory design with additional...
9001568 Testing signal development on a bit line in an SRAM  
An embodiment of the invention discloses a method for testing a memory cell in an SRAM. The number of dummy memory cells on a single dummy word line used to drive the dummy bit lines is selected....
8995176 Dual-port SRAM systems  
Schematic circuit designs for a dual-port SRAM cell are disclosed, together with various layout schemes for the dual-port SRAM cell. The dual-port SRAM cell comprises a storage unit and a...
8982596 Content addressable memory having column segment redundancy  
A CAM device includes a CAM array that can implement column redundancy in which a defective column segment in a selected block can be functionally replaced by a selected column segment of the same...
8964453 SRAM layouts  
Roughly described, the cell layout in an SRAM array is re-arranged such that the gate electrodes for transistors for which flexibility to use one channel length is desired, are formed along a...
8964457 Methods for operating SRAM cells  
A circuit includes a Static Random Access Memory (SRAM) array. An SRAM cell is in the SRAM array and includes a p-well region, a first and a second n-well region on opposite sides of the p-well...
8953354 Semiconductor memory device and method of driving semiconductor memory device  
A semiconductor memory device includes a memory portion that includes i (i is a natural number) sets each including j (j is a natural number of 2 or larger) arrays each including k (k is a natural...
8947900 Stable SRAM cell  
SRAM cells and SRAM cell arrays are described. In one embodiment, an SRAM cell includes a first inverter and a second inverter cross-coupled with the first inverter to form a first data storage...
8929116 Two phase search content addressable memory with power-gated main-search  
Low leakage CAMs and method of searching low leakage CAMs. The method includes performing a pre-search and compare on a small number of pre-search bits with pre-search CAM cells powered to normal...
8929115 XY ternary content addressable memory (TCAM) cell and array  
A ternary content addressable memory (TCAM) is formed by TCAM cells that are arranged in an array. Each TCAM cell includes a first and second SRAM cells and a comparator. The SRAM cells...
8908409 Stable SRAM cell  
SRAM cells and SRAM cell arrays are described. In one embodiment, an SRAM cell includes a first inverter and a second inverter cross-coupled with the first inverter to form a first data storage...
8902624 Content addressable memory  
The present invention provides a content addressable memory capable of higher frequency operation than conventional. When a search enable signal supplied from a search control circuit is asserted,...
8891272 Content addressable memory system  
There is a need to highly integrate a circuit area of content addressable memory (CAM) and ensure faster operation thereof. A priority encoder and row decoder portion shares a row address register...
8885379 High speed magnetic random access memory-based ternary CAM  
The present disclosure concerns a self-referenced magnetic random access memory-based ternary content addressable memory (MRAM-based TCAM) cell comprising a first and second magnetic tunnel...
8885393 Memory array voltage source controller for retention and write assist  
A voltage source controller for a memory array includes an input coupled to a voltage source, an output coupled to one or more memory cells of a memory array, where the output is configured to...
8879334 Semiconductor device having timing control for read-write memory access operations  
A semiconductor device avoids the disturb problem and the collision between write and read operations in a DP-SRAM cell or a 2P-SRAM cell. The semiconductor device 1 includes a write word line WLA...
8873278 Volatile memory elements with soft error upset immunity  
Memory elements are provided that exhibit immunity to soft error upset events when subjected to high-energy atomic particle strikes. The memory elements may each have ten transistors. To overcome...
8848411 Shared stack dual phase content addressable memory (CAM) cell  
A shared stack dual-phase CAM cell is provided. The CAM cell includes at least first and second stacks that share a single pair of pull-down transistors. At least one pair of pull-down transistors...
8848413 Low power register file  
Described is an apparatus which comprises: a memory cell with a data port; and a logic gate, coupled to the data port of the memory cell, to generate a data word-line signal according to data on...
8842475 Configuration memory  
According to one embodiment, a configuration memory includes first and second data lines, a first memory string which comprises at least first and second nonvolatile memory transistors which are...
8837190 System for retaining state data  
According to one embodiment, a system for retaining M bits of state data of an integrated circuit during power down includes M serially coupled scan flip flops divided into M/N groups, where the M...
8837205 Multi-port register file with multiplexed data  
A semiconductor memory storage device comprises an array of storage devices including a plurality of rows of the storage devices and a plurality of columns of the storage devices, a first...
8830732 SRAM cell comprising FinFETs  
A Static Random Access Memory (SRAM) cell includes a first long boundary and a second long boundary parallel to a first direction, and a first short boundary and a second short boundary parallel...
8804392 Content addressable memory chip  
A content addressable memory chip which can perform a high speed search with less error is provided. A match amplifier zone determines coincidence or non-coincidence of search data with data...
8787058 Selectable multi-way comparator  
A method for comparing content addressable memory (CAM) elements is disclosed. Binary values are stored in a pair of CAM elements. A comparison value is provided to a group of comparators, the...
8767488 Content addressable memory having half-column redundancy  
A method and apparatus for performing half-column redundancy in a CAM device is disclosed, capable of replacing a defective half-column in the CAM array with only one half of another column. For...
8743581 Memory devices having break cells  
A representative memory device includes a cell array, at least one break cell that subdivides the cell array into bit cell arrays, and one or more power switches that are electrically coupled to...
8743579 Stable SRAM cell  
SRAM cells and SRAM cell arrays are described. In one embodiment, an SRAM cell includes a first inverter and a second inverter cross-coupled with the first inverter to form a first data storage...
8675397 Cell structure for dual-port SRAM  
The present disclosure provides a dual port static random access memory (SRAM) cell. The dual-port SRAM cell includes a first and second inverters cross-coupled for data storage, each inverter...
8625320 Quaternary content addressable memory cell having one transistor pull-down stack  
Quaternary CAM cells are provided that include a compare circuit having a discharge path between a match line and ground potential, the single discharge path consisting essentially of a single...
8576599 Multi-wafer 3D CAM cell  
A multi-wafer CAM cell in which the negative effects of increased travel distance have been substantially reduced is provided. The multi-wafer CAM cell is achieved in the present invention by...
8570791 Circuit and method of word line suppression  
A word line driver circuit for providing a suppressed word line voltage includes a switch configured to selectively load a word line to a suppressed word line voltage node and a word line charging...
8542514 Memory structure having SRAM cells and SONOS devices  
A memory structure and method to fabricate the same is described. The memory structure includes a first memory cell having a first pair of non-volatile portions. The memory structure also includes...
8514613 Memory elements with a configurable number of ports  
Integrated circuits may include configurable-port memory cells. The configurable-port memory cells may be operable in single-port mode and multiport mode. Each configurable-port memory cell may be...
8462533 System for retaining state data  
According to one embodiment, a system for retaining M bits of state data of an integrated circuit during power down includes M serially coupled scan flip flops divided into M/N groups, where the M...
8441828 Content addressable memory  
The present invention provides a content addressable memory capable of higher frequency operation than conventional. When a search enable signal supplied from a search control circuit is asserted,...
8441829 Stable SRAM cell  
SRAM cells and SRAM cell arrays are described. In one embodiment, an SRAM cell includes a first inverter and a second inverter cross-coupled with the first inverter to form a first data storage...
8369175 Memory elements with voltage overstress protection  
Integrated circuits may include memory elements that are provided with voltage overstress protection. One suitable arrangement of a memory cell may include a latch with two cross-coupled...
8363470 Memory device of the electrically erasable and programmable type, having two cells per bit  
The memory device includes a memory cell unit of the electrically erasable and programmable non-volatile type including two memory cells respectively connected to two bit lines via two bit line...
8363456 Semiconductor device  
To improve reliability of a semiconductor device having an SRAM. The semiconductor device has a memory cell including six n-channel type transistors and two p-channel type transistors formed over...
8325506 Devices and methods for comparing data in a content-addressable memory  
The invention provides a content-addressable memory cell formed by two transistors that are configured so that one of the transistors is for storing a data bit and the other for is storing the...
8315078 Power saving static-based comparator circuits and methods and content-addressable memory (CAM) circuits employing same  
Static-based comparators and methods for comparing data are disclosed. The static-based comparator is configured to selectively switch at least one comparator output in response to a comparison of...
8310853 Layout structure of bit line sense amplifiers for a semiconductor memory device  
A layout structure of bit line sense amplifiers for use in a semiconductor memory device includes first and second bit line sense amplifiers arranged to share and be electrically controlled by a...
8264862 Low power SRAM based content addressable memory  
An apparatus comprising a memory array and a plurality of processing circuits. The memory array may be configured to store a plurality of data bits in a plurality of rows and a plurality of...
8233302 Content addressable memory with concurrent read and search/compare operations at the same memory cell  
A content addressable memory (CAM) device includes an array of memory cells arranged in rows and columns; compare circuitry configured to indicate match results of search data presented to each...
8218353 Memory element circuitry with stressed transistors  
Integrated circuits with memory elements are provided. The memory elements may be arranged in a memory block. The memory block may include cross-coupled inverters that store data. The stored data...
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