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7567482 Block redundancy implementation in heirarchical ram's  
The present invention relates to a system and method for providing redundancy in a hierarchically memory, by replacing small blocks in such memory. The present invention provides such redundancy...
7567471 High speed fanned out system architecture and input/output circuits for non-volatile memory  
In various embodiments, a plurality of non-volatile memory devices, such as NAND flash memory device, may be connected to a host controller device in a fanned out configuration that allows each of...
7525871 Semiconductor integrated circuit  
Fuse data is supplied to each of a plurality of function blocks through a transfer path using shift registers. When the reliability of fuse elements is low, there is a possibility that a part of...
7495993 Onboard data storage and method  
A semiconductor memory device and an associated method suitable for use in specific applications with predictable memory access pattern, such as in a capsule camera. The memory device takes...
7492623 Option circuits and option methods of semiconductor chips  
An option circuit of a semiconductor chip includes a first option circuit that is set before packaging the semiconductor chip to generate a first option signal; a second option circuit that is set...
7477564 Method and apparatus for redundant memory configuration in voltage island  
A method and apparatus to configure redundant memory elements in a system on a chip (SoC) having discrete voltage domains (islands). A plurality of memories are provided for each voltage island,...
7447870 Device for identifying data characteristics for flash memory  
A highly efficient data characteristic identification device for flash memory is provided, including an instruction register, a plurality of auxiliary controllers, a data register, an address...
7433246 Flash memory device capable of storing multi-bit data and single-big data  
There is provided a flash memory device capable of manipulating multi-bit and single-bit data. The flash memory device can include a memory cell array with a plurality of memory blocks. The flash...
7426153 Clock-independent mode register setting methods and apparatuses  
Mode register setting methods and apparatuses for semiconductor devices are provided in order to suppress a limit in the frequency at which a mode register of a semiconductor device operates from...
7366031 Memory arrangement and method for addressing a memory  
A memory arrangement includes a plurality of switching elements arranged in the form of a binary tree. The memory elements are supplied with data to be stored by the switching elements coupled to...
7355917 Two-dimensional data memory  
A two-dimensional data memory ( 1 ) comprising memory elements which are arranged in rows and columns, which are designed to store in each case one data word, which in the row direction and in the...
7330378 Inputting and outputting operating parameters for an integrated semiconductor memory device  
An integrated semiconductor memory device includes a control circuit with a mode register to store operating parameters, as well as further registers to store further operating parameters. An...
7315479 Redundant memory incorporating serially-connected relief information storage  
A relief processing section which performs a relief process with respect to a redundant memory comprises a plurality of defect relief sections each having shift register circuits (relief...
7310262 Ferroelectric memory capable of continuously fast transferring data words in a pipeline  
A storage device including a ferroelectric memory cell array including a plurality of memory cells; sense amplifiers connected to the bit lines and selected by a column address; an internal counter...
7307913 Clock control device for toggling an internal clock of a synchronous DRAM for reduced power consumption  
A clock control device includes a set circuit for triggering an input address in response to an internal command signal to output a first address, a shift register including a plurality of...
7304906 Method of controlling mode register set operation in memory device and circuit thereof  
Disclosed is a method of controlling an MRS operation in a memory device which can prevent an unnecessary MRS operation due to a malfunction of the memory device at a time when the memory device...
7305058 Multi-standard clock rate matching circuitry  
Clock rate matching circuitry is provided to buffer data between two clock domains that may have slightly different frequencies. To facilitate supporting a wide range of different communication...
7277351 Programmable logic device memory elements with elevated power supply levels  
Programmable logic device integrated circuits are provided. The programmable logic device integrated circuits contain programmable core logic powered at a programmable core logic power supply...
7227812 Write address synchronization useful for a DDR prefetch SDRAM  
Disclosed herein are exemplary embodiments of an improved write address shift register structure useful for example in a DDR3 DRAM having read/write latency. The disclosed shift register structure...
7216215 Data access method applicable to various platforms  
A data access method uses variable mask data and shift amount to write data into or read data from a data storage zone. The mask data and shift amount are determined according to starting and end...
7203109 Device and method for detecting corruption of digital hardware configuration  
A device for verifying hardware in a circuit arrangement that includes one or more configuration elements ( 106 ) operable to configure hardware elements ( 108 ) that are electrically coupled by...
7187604 Semiconductor memory  
A shift register includes plural latches corresponding to normal word lines of normal memory cell rows and a redundancy word line of a redundancy memory cell row, respectively, in order to...
7180797 Reduced power registered memory module and method  
A registered memory module includes a plurality of flip-flops having respective data terminals, respective clock terminals receiving a clock signal and output terminals coupled to a plurality of...
7145832 Fully-hidden refresh dynamic random access memory  
A composite gate detects whether an internal array is in a selected state and an internal row activation signal is activated in accordance with a timing relationship between an output signal of the...
7116578 Non-volatile memory device and data storing method  
In a card storage device containing a non-volatile memory and a buffer memory, the buffer memory includes a plurality of banks. Data is transferred sequentially from a host CPU to the banks of the...
7076600 Dual purpose interface using refresh cycle  
A method and system for optimizing use of signal paths on a DRAM interface. Signal paths that have a ‘don't care’ status during DRAM refresh are assigned to communication with another device....
7061783 Content addressable memory (CAM) capable of finding errors in a CAM cell array and a method thereof  
A method of finding errors in a content addressable memory (CAM) and a CAM cell array, the CAM being capable of finding errors in the CAM cell array, is disclosed. The CAM includes the CAM cell...
7061828 Fully-hidden refresh dynamic random access memory  
A composite gate detects whether an internal array is in a selected state and an internal row activation signal is activated in accordance with a timing relationship between an output signal of the...
7061821 Address wrap function for addressable memory devices  
The invention is a selectable function that permits the address portion of data words to be separated from the storable content portion and that address portion to be used for different purposes...
7057946 Semiconductor integrated circuit having latching means capable of scanning  
Circuits have a certain function. A plurality of first registers are connected in series, and shift stored data to respective adjacent registers in sequence. A plurality of second registers are...
7054218 Serial memory address decoding scheme  
A decode circuit for a memory that uses “sequential addressing” includes a series of decoders form a shift register that may be used to provide either wordlines or column select lines for...
7046537 Reduced signal swing in bit lines in a CAM  
A Content Addressable Memory device with a bit line that is driven between first and second voltage levels depending on the state of a logic signal applied thereto. The magnitude of the voltage...
7027348 Power efficient read circuit for a serial output memory device and method  
An integrated circuit memory device has a plurality of memory cells arranged in a plurality of arrays. Each array has a plurality of rows, and a plurality of column lines, and a plurality of row...
7016242 Semiconductor memory apparatus and self-repair method  
In a memory unit provided by the present invention, unit blocks are laid out to form a block matrix. Each of the unit blocks has a plurality of memory cells arranged to form a cell matrix and a...
7009886 Integrated circuit memory device with bit line pre-charging based upon partial address decoding  
An integrated circuit memory device has an array of memory cells arranged in a plurality of rows and columns and a plurality of row lines and a plurality of column lines. Cells arranged in the same...
6986072 Register capable of corresponding to wide frequency band and signal generating method using the same  
A maximum value of the number of mounted memory devices is assumed, and a value of an external delay replica is fixed and set. A desired frequency band is divided into a plurality of sub-frequency...
6947307 Package map data outputting circuit of semiconductor memory device and method for outputting package map data  
A package map data outputting circuit of a semiconductor memory device embedded with a test circuit and a method for the same. In order to improve the reliability of package map data and easily...
6947301 Content addressable memory (CAM) device employing a recirculating shift register for data storage  
A content addressable memory (CAM) device is described including a plurality of storage locations, each arranged as a recirculating shift register, and plurality of bit comparators each coupled to...
6948014 Register for the parallel-serial conversion of data  
Register for the parallel-serial conversion of data having a plurality of cyclically driven shift registers ( 2 ), each comprising series-connected data holding elements ( 3 ), each data holding...
6885606 Synchronous semiconductor memory device with a plurality of memory banks and method of controlling the same  
A synchronous semiconductor memory device includes a plurality of memory banks which read data from memory cells and write data into the memory cells, a command decoder circuit which receives a...
6839285 Page by page programmable flash memory  
An integrated circuit memory includes a FLASH memory including a circuit for recording a word presented on its input without the possibility of recording simultaneously several words in parallel....
6819618 Semiconductor memory device capable of executing refresh operation according to refresh space  
A semiconductor memory device includes a memory having a predetermined number of divided memory spaces, a register that stores data indicating whether a refresh operation is required or not with...
6788617 Device for generating memory address and mobile station using the address for writing/reading data  
A device for generating memory addresses is provided that is suitable for generating memory addresses transposed in row/column directions with reference to a data successively stored therein along...
6731537 Non-volatile memory device and data storing method  
In a card storage device containing a non-volatile memory and a buffer memory, the buffer memory includes a plurality of banks. Data is transferred sequentially from a host CPU to the banks of the...
6714464 System and method for a self-calibrating sense-amplifier strobe  
A system and method for self-calibration of the strobe timing of the sense-amplifiers of a RAM array. In one method example, the timing of two sense amplifiers used to read the bit-lines of the RAM...
6711494 Data formatter for shifting data to correct data lanes  
A data formatter includes a shift register and a pointer manager. The shift register receives data from a providing RAM and shifts that data in response to reading data from the providing RAM and...
6707726 Register without restriction of number of mounted memory devices and memory module having the same  
First and second pre-processing flip-flops latch a command/address signal inputted to a register by a clock having a frequency of ½ of an external clock signal and an inverse clock thereof. Thus,...
6646943 Virtual static random access memory device and driving method therefor  
The present invention discloses a virtual static random access memory device that uses a dynamic memory cell and refreshes data of the memory cell, and a driving method therefor. When data of the...
6639850 Semiconductor integrated circuit having latching means capable of scanning  
A plurality of first registers are connected in series, and shift stored data to respective adjacent registers in sequence. A plurality of second registers are connected in series, and shift stored...
6629190 Non-redundant nonvolatile memory and method for sequentially accessing the nonvolatile memory using shift registers to selectively bypass individual word lines  
A memory including a plurality of memory word lines and a sequential addressing circuit is provided. The sequential addressing circuit comprises at least one sequential shift register including at...
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