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7613061 Method and apparatus for idle cycle refresh request in DRAM  
Generally, methods and apparatus are provided for idle cycle refresh request in a dynamic random access memory. According to one aspect of the invention, a dynamic random access memory is refreshed...
7609567 System and method for simulating an aspect of a memory circuit  
A system and method are provided for simulating an aspect of a memory circuit. Included is an interface circuit that is in communication with a plurality of memory circuits and a system. Such...
7609553 NAND flash memory device with burst read latency function  
A NAND flash memory device may include an interface block which receives an external read enable signal to output an internal clock signal during a read operation. The NAND flash memory device may...
7599247 Memory and method of writing data  
Semiconductor memory devices 10 are each furnished with a memory array 100 having an EEPROM array 101 and a mask ROM array 102 . Identifying information for identifying each semiconductor...
7590026 Access to printing material container  
The present invention provides a storage device that enables identification data to be readily rewritten and ensures normal completion of a data writing operation in a short time period. In the...
7580322 High speed programming for nonvolatile memory  
A nonvolatile memory device is programmed by selectively scanning input data bits to detect data bits to be programmed, and programming the detected data bits. The detected data bits may be...
7573779 Semiconductor memory and electronic device  
A semiconductor memory that reduces the power consumption of a memory cell array without exercising control by a microprocessor. The semiconductor memory comprises a memory cell array, a switch for...
7570541 Semiconductor memory device  
A word control circuit activates word lines corresponding to a start row address and a next row address overlapping in the continuous mode. Accordingly, even in the case where the start address...
7567482 Block redundancy implementation in heirarchical ram's  
The present invention relates to a system and method for providing redundancy in a hierarchically memory, by replacing small blocks in such memory. The present invention provides such redundancy...
7567471 High speed fanned out system architecture and input/output circuits for non-volatile memory  
In various embodiments, a plurality of non-volatile memory devices, such as NAND flash memory device, may be connected to a host controller device in a fanned out configuration that allows each of...
7564739 Storage cell design evaluation circuit including a wordline timing and cell access detection circuit  
A storage cell design evaluation circuit including a wordline timing and cell access detection circuit provides accurate information about state changes in static storage cells. A storage cell test...
7551514 Semiconductor memory utilizing a method of coding data  
A semiconductor memory device utilizing a data coding method in an initial operation. The device includes a plurality of counters that count the number of data bits and flag information data bits....
7535772 Configurable data path architecture and clocking scheme  
Data paths ( 100 and 900 ) can be configured to accommodate two or four burst data sequences, with a data value being input/output each half clock cycle. A data sequence can be a fixed order or...
7529139 N-port memory circuits allowing M memory addresses to be accessed concurrently and signal processing methods thereof  
Method and memory circuits capable of allowing M memory addresses of an N-port memory to be accessed concurrently, wherein N and M both are a natural number, and M is larger than N. Accordingly, a...
7522470 Semiconductor memory device  
When the input write data is a value of a value greater than the existing data of the memory array 100 , the semiconductor memory device enables writing of input write data to the memory array ...
7508731 Semiconductor memory device with a fixed burst length having column control unit  
The present invention relates to a semiconductor memory device with a fixed burst length, including a column control circuit, the semiconductor memory device including: a command decoder decoding...
7495993 Onboard data storage and method  
A semiconductor memory device and an associated method suitable for use in specific applications with predictable memory access pattern, such as in a capsule camera. The memory device takes...
7489583 Constant-weight-code-based addressing of nanoscale and mixed microscale/nanoscale arrays  
Various embodiments of the present invention include methods for determining nanowire addressing schemes and include microscale/nanoscale electronic devices that incorporate the nanowire addressing...
7477570 Sequential access memory with system and method  
A sequential access memory (“SAM”) device, system and method is provided that includes a memory array configured to store a group of bytes on each of a plurality of rows. A plurality of...
7474587 Flash memory device with rapid random access function and computing system including the same  
A flash memory device includes a memory cell array, an address buffer circuit including address buffers, each address buffer configured to store an address for a random read operation, a read...
7471586 Semiconductor memory device which controls refresh of a memory array in normal operation  
A semiconductor memory device is comprised of a refresh counter for sequentially generating a count value indicating one or more row addresses corresponding to one or more word lines to be...
7466623 Pseudo SRAM capable of operating in continuous burst mode and method of controlling burst mode operation thereof  
A pseudo SRAM which can perform read and write operations of data in a continuous burst mode in such a manner that it continuously generates burst row and column address signals, which gradually...
7460412 Flash memory device and erasing method thereof  
A method of post-programming a flash memory device includes the steps of: post-programming memory cells of a selected word line in a predetermined unit; determining, after incrementing an address...
7450462 System and memory for sequential multi-plane page memory operations  
A system and method for performing memory operations in a multi-plane flash memory. Commands and addresses are sequentially provided to the memory for memory operations in memory planes. The memory...
7433260 Memory device and print recording material receptacle providing memory device  
The operation code decoder 204 having received an access enable signal EN acquires and decodes the command, and sends the decoded command to the read/write controller 206 . In the event that the...
7428178 Memory circuit containing a chain of stages  
A memory circuit is provided that includes at least one chain of at least three stages each having a data input, a data output, and a control signal input. Each of the stages between the first...
7397727 Write burst stop function in low power DDR sDRAM  
A write burst stop command function is provided for a semiconductor memory device, and in particular for a memory device having a write latency, such as is common in a low power double data rate...
7394718 Semiconductor memory device having a global data bus  
There is provided a semiconductor design technology, particularly, a bus line arrangement method of global data bus in the semiconductor memory device. According to the invention, skew by lines can...
7394710 Auto-recovery fault tolerant memory synchronization  
Automatic fault recovery of upsets in a memory controller are provided to minimize data loss. In addition to memory control, the present invention allows for the incorporation of majority voting...
7391672 Sequential memory and accessing method thereof  
A method for accessing a memory sequentially. The memory has (m+1) bit lines and at least one row of transistors, wherein m is a positive integer. This method includes the following steps. First,...
7355917 Two-dimensional data memory  
A two-dimensional data memory ( 1 ) comprising memory elements which are arranged in rows and columns, which are designed to store in each case one data word, which in the row direction and in the...
7353356 High speed, low current consumption FIFO circuit  
A FIFO circuit includes a write counter circuit, a memory circuit, a read counter circuit and a selector circuit. The write counter circuit counts a write clock signal during a valid period of...
7349277 Method and system for reducing the peak current in refreshing dynamic random access memory devices  
A dynamic random access memory device includes a mode register that is programmed with a delay value. In some embodiments, a offset code is also stored in the memory device. The memory device uses...
7349246 Initial firing method and phase change memory device for performing firing effectively  
In a firing method of a phase change memory device and a phase change memory capable of effectively performing a firing operation, the phase change memory device includes a plurality of memory cell...
7327632 Interface circuit  
An interface apparatus having a first and a second buffer storage unit, the first buffer storage unit being associated with a first domain and the second buffer storage unit being associated with a...
7315479 Redundant memory incorporating serially-connected relief information storage  
A relief processing section which performs a relief process with respect to a redundant memory comprises a plurality of defect relief sections each having shift register circuits (relief...
7304899 Integrated semiconductor memory  
An integrated semiconductor memory includes programmable elements, which are arranged in a continuous region on a chip area of the integrated semiconductor memory. Operating parameters, for...
7266028 Method and apparatus for bit mapping memories in programmable logic device integrated circuits during at-speed testing  
Programmable logic devices may use shadow memory for gathering diagnostic information while testing memory blocks. Memory block testing may be performed at any clock speed allowed during normal...
7263014 Semiconductor memory device having N-bit prefetch type and method of transferring data thereof  
A semiconductor memory device in which only global I/O buses, which receive one or more data groups that must be output first among a N number of data groups that are prefetched in a N-bit prefetch...
7254076 Semiconductor memory device for improving response margin of redundancy flag signal and redundancy driving method for the same  
A burst mode compatible semiconductor memory device having a redundancy memory adapted to repair a normal memory is disclosed. Response margin for a redundancy flag signal and redundancy driving...
7254090 Semiconductor memory device  
An internal address generating circuit sequentially generates internal addresses in the burst read operation, with an external address being set as an initial value. A memory core has plural memory...
7239573 Method of storing data in blocks per operation  
The present invention is to provide a method of storing data for driving an MMC or SD under an operating system (e.g., Linux), which comprises the steps of collecting data in a plurality of...
7236407 Flash memory architecture for optimizing performance of memory having multi-level memory cells  
A flash memory device having a pipelined RAS/CAS architecture is logically organized as an array of rows and columns of multi-bit flash memory cells each capable of being selectively programmed to...
7221609 Fine granularity DRAM refresh  
A method, device, and system are included. In one embodiment, the method included issuing a single row refresh command for a first row in a memory starting at a target address, incrementing a row...
7215580 Non-volatile memory control  
According to an embodiment of the present invention, there is provided a method and apparatus for use in a memory system having a non-volatile memory and a controller for limiting the number of...
7196968 Method of driving data lines, and display device and liquid crystal display device using method  
A method of driving source lines is arranged as follows: One output signal line S 61 of a source driver is connected to a plurality of lines corresponding to respective source lines SR 7 through...
7196962 Packet addressing programmable dual port memory devices and related methods  
In a packet addressing method, one or more memory blocks are selected from a plurality of memory blocks and one or more data I/O pads are selected from a plurality of data I/O pads via which data...
7184322 Semiconductor memory device and control method thereof  
A semiconductor memory device has common terminals shared between a part or all of address terminals for receiving n bits of an address signal and data terminals for outputting a data signal with...
7177999 Reading extended data burst from memory  
A method for reading, from a semiconductor memory, data having a data burst length greater than two includes, beginning at a first time, receiving, on an address bus, a first address part...
7170808 Power saving refresh scheme for DRAMs with segmented word line architecture  
Techniques and apparatus that may be utilized to reduce current consumption during refresh cycles of DRAM devices that utilize wordline segments are provided. Rather than activate and subsequently...
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