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7624238 Memory controller and data processing system  
A memory controller and data processor have their operation mode switched from the page-on mode for high-speed access to a same page to the page-off mode in response to consecutive events of access...
7616507 Microprocessor boot-up controller, nonvolatile memory controller, and information processing system  
A memory system including a nonvolatile semiconductor memory device and a controller. The memory device includes a plurality of word lines; and a plurality of memory cells each connected to a...
7577059 Decoding control with address transition detection in page erase function  
Circuits and methods are provided for controlling multi-page erase operations in flash memory. The page address of each address of a multi-page erase operation is latched in wordline decoders. A...
7554874 Method and apparatus for mapping memory  
A memory mapping method is provided for writing block data composed of a plurality of lines in first and second memories, each memory including at least two banks of the same number. The method...
7548468 Semiconductor memory and operation method for same  
A bit line resetting signal is supplied to the gate of an nMOS transistor (or a precharge circuit) which connects a bit line with a precharge voltage line. The high-level voltage of the bit line...
7542350 Methods of restoring data in flash memory devices and related flash memory device memory systems  
Methods for setting a read voltage in a memory system which comprises a flash memory device and a memory controller for controlling the flash memory device, comprise sequentially varying a...
7539052 Non-volatile multilevel memory cell programming  
Embodiments of the present disclosure provide methods, devices, modules, and systems for programming an array of non-volatile multilevel memory cells to a number of threshold voltage ranges. One...
7525842 Increased NAND flash memory read throughput  
A method of reading sequential pages of flash memory from alternating memory blocks comprises loading data from a first page into a first primary data cache and a second page into a second primary...
7453731 Method for non-volatile memory with linear estimation of initial programming voltage  
In a non-volatile memory, a selected page on a word line is successively programmed by a series of voltage pulses of a staircase waveform with verifications in between the pulses until the page is...
7400549 Memory block reallocation in a flash memory device  
A non-volatile memory device has the pages of a certain memory block reallocated to other blocks in order to increase decrease disturb and increase reliability. Each of the reallocation blocks that...
7400531 Semiconductor integrated circuit device  
A semiconductor integrated circuit device has a page buffer, several memory cells to which data is written in accordance with write data stored in the page buffer, and an accumulating counter. The...
7391632 Apparatus of selectively performing fast hadamard transform and fast fourier transform, and CCK modulation and demodulation apparatus using the same  
A Fast Fourier Transform (FFT) apparatus for selectively performing Fast Hadamard transform (FHT), and a complementary code keying (CCK) modulation/demodulation apparatus using the same. An OFDM...
7369432 Method for implementing a counter in a memory with increased memory efficiency  
A method for implementing a counter in memory, e.g., non-volatile memory such as flash memory. A first number of first binary values indicating a first portion of a current number of the counter in...
7310284 Page access circuit of semiconductor memory device  
A page access circuit of a semiconductor memory device comprises a page address detecting unit configured to detect transition of a page address in response to a page address control signal so as...
7212426 Flash memory system capable of inputting/outputting sector data at random  
A flash memory system capable of inputting/outputting data in units of sectors at random. The flash memory system includes a flash memory (a cell array), a buffer memory, a random data input/output...
7123538 Semiconductor memory device for improving access time in burst mode  
A semiconductor memory device is disclosed. A block unit is divided into memory mats based on an internal address. In the case where the internal address is “1”, data are read in ascending...
7079448 Word-programmable flash memory  
The present invention relates to a memory in integrated circuit comprising a central Flash-type memory comprising memory cells forming pages, a buffer memory capable of storing binary words, and a...
7016226 Semiconductor memory device for storing multivalued data  
Data storage circuits are connected to the bit lines in a one-to-one correspondence. A write circuit writes the data on a first page into a plurality of first memory cells selected simultaneously...
6992943 System and method for performing partial array self-refresh operation in a semiconductor memory device  
Systems and methods for performing a PASR (partial array self-refresh) operation wherein a refresh operation for recharging stored data is performed on a portion (e.g., ½ ¼, ⅛, or 1/16) of one...
6990044 Composite memory device  
The present invention relates to a composite memory device comprising first through third memory devices, a memory bus, and first through third memory controllers. The first memory device is an...
6839285 Page by page programmable flash memory  
An integrated circuit memory includes a FLASH memory including a circuit for recording a word presented on its input without the possibility of recording simultaneously several words in parallel....
6785190 Method for opening pages of memory with a single command  
An efficient invention for opening two pages of memory for a DRAM are discussed.
6745279 Memory controller  
A memory controller is disclosed, in which upon receipt of an access request from a device, the memory controller activates a page designated by a row address of a first bank at a predetermined...
6724682 Nonvolatile semiconductor memory device having selective multiple-speed operation mode  
Disclosed is a nonvolatile semiconductor memory device having selective multiple-speed operation modes selected by simple options. The nonvolatile semiconductor memory device includes a memory cell...
6724670 Shared redundancy for memory having column addressing  
A shared redundancy prefetch scheme to provide a reduced number of fuses. DDR SDRAMs allow burst addressing at various burst lengths. DDR SDRAMs generally implement LEFT and RIGHT segment column...
6683817 Direct memory swapping between NAND flash and SRAM with error correction coding  
Memory architectures and techniques that support direct memory swapping between NAND Flash and SRAM with error correction coding (ECC). In a specific design, a memory architecture includes a first...
6675269 Semiconductor device with memory controller that controls page mode access  
A memory controller and data processor have their operation mode switched from the page-on mode for high-speed access to a same page to the page-off mode in response to consecutive events of access...
6496446 Semiconductor memory device having burst readout mode and data readout method  
A semiconductor memory having burst mode operation includes a memory cell array, a sense amplifier circuit determining data of memory cells, a latch circuit having first and second latch groups and...
6487132 Integrated circuit memory devices having multiple input/output buses and precharge circuitry for precharging the input/output buses between write operations  
Integrated circuit memory devices include precharge controller circuit, which generates a precharge control signal in response to completion of a write operation on a first input/output bus. A...
6477101 Read-ahead electrically erasable and programmable serial memory  
A serial input/output memory is able to read data in the memory upon reception of a partial read address in which there are N least significant bits lacking to form a complete address. The...
6449209 Semiconductor memory device comprising more than two internal banks of different sizes  
A semiconductor memory device includes a plurality of internal banks of different sizes. The internal banks are suitable for and correspond to the memory needs of a plurality of master devices....
6404250 On-chip circuits for high speed memory testing with a slow memory tester  
A memory system on a semiconductor body is tested by testing components formed on the semiconductor body. A programmable clock signal generator receives an external clock signal and selectively...
6278636 Nonvolatile semiconductor memory device having improved page buffers  
Disclosed herein is a nonvolatile semiconductor memory device which comprises a memory cell array, page buffers and Y-pass gate circuit. Each page buffer according to the present invention contains...
6269430 Method for controlling a process of writing data sent by a central processing unit to a memory by using a central processing unit interface  
A method for a CPU interface to control a writing process that writes data sent from a CPU to a memory. The CPU interface controls the writing process through steps mainly including receiving a...
6205106 Memory card recording/reproducing with two light sources and a light value matrix  
Method of storing and retrieving information by exposing cells of a storage medium to a first beam of light having a first set of properties affecting the optical properties of said storage medium,...
6154419 Method and apparatus for providing compatibility with synchronous dynamic random access memory (SDRAM) and double data rate (DDR) memory  
A method and apparatus for providing compatibility with synchronous dynamic random access memory (SDRAM) and double data rate (DDR) memory is provided. While memory accessing agents, such a...
6034919 Method and apparatus for using extended-data output memory devices in a system designed for fast page mode memory devices  
A memory system including a memory controller that operates in conformity with fast page mode (FPM) memory devices and an extended-data output (EDO) memory device configured to operate with the FPM...
6026055 Burst page access unit usable in a synchronous DRAM and other semiconductor memory devices  
A burst page access unit for a semiconductor memory device which has a plurality of memory cell arrays for storing bit data therein. The burst page access unit comprises a row decoder for decoding...
6026053 Photorefractive read-only optical memory apparatus using phase, frequency, and angular modulation  
The present invention stores and retrieves digital information by altering the phase transmission characteristics of a multiple layer phase recording by modulating the carrier frequency and the...
5881016 Method and apparatus for optimizing power consumption and memory bandwidth in a video controller using SGRAM and SDRAM power reduction modes  
The display controller of the present invention reduces power consumption by suppressing clock signals to a display memory (comprising SGRAM or SDRAM) between screen refreshes and memory accesses....
5881017 Synchronous semiconductor memory device allowing fast operation in either of prefetch operation and full page mode operation  
SDRAM 1000 outputs data, in a 2-bit prefetch operation, by simultaneously selecting two columns in memory cell array banks A0 and A1 in accordance with column select signals YE0-YEk and YO0-YOk...
5757719 Page-mode memory device with multiple-level memory cells  
A page-mode semiconductor memory device comprises a matrix of memory cells arranged in rows and columns, each row forming a memory page of the memory device and comprising at least one group of...
5737276 Memory device with fast extended data out (EDO) mode and methods of operation therefor  
A memory device having normal and extended data out (EDO). modes includes an array of memory cells arranged in plurality of rows and columns, first and second data latches which store data, a...
5715198 Output latching circuit for static memory devices  
An output latching circuit for low power static memory devices guarantees glitch-free operation and high performance. The output latching circuit uses first and second latches respectively...
5682354 CAS recognition in burst extended data out DRAM  
An integrated memory circuit is described which can be operated in a burst access mode. The memory circuit includes an address counter which changes column addresses in one of a number of...
5673233 Synchronous memory allowing early read command in write to read transitions  
A synchronous random access memory, such as a synchronous dynamic random access memory or a synchronous graphic random access memory, is responsive to command signals and includes a bank memory...
5654936 Control circuit and method for controlling a data line switching circuit in a semiconductor memory device  
The present invention relates to a control circuit and method for controlling a data line switching circuit in a semiconductor memory device having a memory cell array, a row decoder for...
5644549 Apparatus for accessing an extended data output dynamic random access memory  
An apparatus for accessing an extended data output dynamic random access memory (EDO DRAM) is disclosed. A conventional fast page mode (FPM) DRAM is converted by the present invention to conform to...
5535174 Random access memory with apparatus for reducing power consumption  
A random access memory (RAM) having an array of memory cells the signal lines to which are activatable by corresponding current sources. The memory is divided into "pages", and control pulses are...
5511035 Optical random access memory having diffractive simplex imaging lens  
An optical memory stores data in an optical data layer capable of selecting altering light such as by changeable transmissivity. Data is organized into a plurality of regions or patches (called...
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