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8184494 |
Cell inferiority test circuit
A cell inferiority test circuit includes a compression data generator configured to compress selected data in response to selection signals and to generate compression data including information...
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8184501 |
Systems and methods for stretching clock cycles in the internal clock signal of a memory array macro
Systems and methods for stretching clock cycles of the internal clock signal of a memory array macro to allow more time for a data access in the macro than the period of an external clock signal....
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8180939 |
Memory devices implementing clock mirroring scheme and related memory systems and clock mirroring methods
A memory device is configured to operate in first and second data input/output modes. The memory device includes a first electrode pad, a second electrode pad, a clock signal line, a first...
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8179733 |
Semiconductor integrated circuit device
A clock-generating circuit for forming internal clock signals by comparing a signal obtained by delaying, through a variable delay circuit, an input clock signal input through an external terminal...
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8174917 |
Semiconductor memory for disconnecting a bit line from sense amplifier in a standby period and memory system including the semiconductor memory
Each memory block has a plurality of memory cells, and word lines and bit lines connected to the memory cells. Precharge switches connect the bit lines to a precharge line. A switch control circuit...
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8174915 |
Semiconductor memory device and method of testing the same
A device and a method controlling the device are provided. A first command is supplied to the device in synchronization with a clock signal of a first frequency. The first command is to have the...
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8169836 |
Buffer control signal generation circuit and semiconductor device
A buffer control signal generation circuit includes a burst start signal generator, a command decoder, a burst controller, and a burst column controller. The burst start signal generator shifts a...
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8169840 |
Address latch circuit and semiconductor memory apparatus using the same
An address latch circuit of a semiconductor memory apparatus includes a control signal generating section configured to generate a control signal in response to an external command signal and a RAS...
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8169850 |
Forming multiprocessor systems using dual processors
In one embodiment, link logic of a multi-chip processor (MCP) formed using multiple processors may interface with a first point-to-point (PtP) link coupled between the MCP and an off-package agent...
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8169841 |
Strobe apparatus, systems, and methods
A strobe signal is received in a device and execution of an operation in the device is delayed when the strobe signal includes a preamble. Additional apparatus, systems, and methods are disclosed.
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8169847 |
Semiconductor memory apparatus and refresh control method of the same
A semiconductor memory apparatus and refresh control method are presented. The semiconductor memory apparatus includes a memory cell block composed of a multiplicity of floating body cell (FBC)...
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8164372 |
Semiconductor device having level shift circuit, control method thereof, and data processing system
To include a first level shift circuit that converts a first internal clock signal having an amplitude value of a first voltage into a second internal clock signal having an amplitude value of a...
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8164963 |
Semiconductor memory device
A semiconductor memory device includes: a first strobe signal generation unit configured to generate a first rising strobe signal in response to a rising DLL clock signal; a second strobe signal...
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8164975 |
Data capture system and method, and memory controllers and devices
Embodiments of a data capture system and method may be used in a variety of devices, such as in memory controllers and memory devices. The data capture system and method may generate a first set of...
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8164974 |
Memory circuits, systems, and method of interleaving accesses thereof
An interleaved memory circuit includes a first memory bank having a first memory cell. A first local control circuit is coupled with the first memory bank. A second memory bank includes a second...
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8159887 |
Clock synchronization in a memory system
A system and method for synchronizing a strobed memory system 10. During memory read and/or memory write operations the corresponding data strobe is sampled at the data destination 50/55 according...
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8159893 |
Data flow control in multiple independent port
A system includes a memory controller and a plurality of memory devices connected in-series that communicate with the memory controller. Each of the memory devices has multiple independent serial...
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8154933 |
Mode-register reading controller and semiconductor memory device
A mode-register reading controller includes a switching signal generator, first and second transmitters, and a control signal generator. The switching signal generator generates a switching signal...
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8154934 |
Semiconductor memory device and memory system having the same
A semiconductor memory device is disclosed. The semiconductor device includes a memory cell array, a clock signal generator configured to receive an external clock signal from the outside of the...
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8154932 |
Increasing efficiency of memory accesses by selectively introducing a relative delay between the time that write addresses are provided to the memory and the time that write data is provided to the memory
Systems and methods for reducing delays between successive write and read accesses in multi-bank memory devices are provided. Computer circuits modify the relative timing between addresses and data...
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8149644 |
Memory system and method that changes voltage and frequency
The memory system includes a semiconductor memory that has an internal circuit, which operates according to a first power supply voltage, and a memory input/output circuit coupled to the internal...
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8149636 |
Semiconductor memory device with pulse width determination
A semiconductor memory device includes a reset signal generating unit configured to generate a reset control signal by delaying a column command signal by an amount of time varying proportional to...
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8151010 |
Memory devices implementing clock mirroring scheme and related memory systems and clock mirroring methods
A memory device is configured to operate in first and second data input/output modes. The memory device includes a first electrode pad, a second electrode pad, a clock signal line, a first...
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8149645 |
Synchronous global controller for enhanced pipelining
The present invention relates to a system and method for processing the read and write operations in a memory architecture. The system processing the read and write operations includes at least one...
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8149643 |
Memory device and method
A memory device and method may include separating alternating read and write accesses to different banks of a memory device.
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8144533 |
Compensatory memory system
A compensatory memory system is described. This memory system substantially improves performance by adapting an associated delay in a way that optimizes circuit performance.
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8144542 |
Semiconductor memory apparatus and method for operating the same
A semiconductor memory apparatus includes a clock input unit configured to receive a system clock and a data clock, a data clock phase regulation unit configured to regulate a frequency of the data...
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8144528 |
Memory with data control
In an embodiment, a memory device comprises memory, a first data link, a first input, a second input, a second data link, a first output and a second output. The first data link is configured to...
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8144529 |
System and method for delay locked loop relock mode
Embodiments of the present invention describe a memory device comprising a delay line and a feedback circuit coupled to the delay line. The feedback circuit has the capability to adjust a delay...
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8144531 |
Latency control circuit, semiconductor memory device including the same, and method for controlling latency
A latency control circuit includes a path calculator configured to calculate a delay value of a path that an input signal is to go through inside a chip and output the delay value as path...
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8139429 |
Output enable signal generating circuit and method of semiconductor memory apparatus
An output enable signal generating circuit for a semiconductor memory apparatus includes an output control unit configured to receive CAS latency information and to generate an output control...
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8134876 |
Data input/output apparatus and method for semiconductor system
A semiconductor memory device includes: a strobe signal reception unit configured to receive a strobe signal and generate a tracking clock signal; a clock reception unit configured to receive a...
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8134886 |
Method and apparatus for reducing oscillation in synchronous circuits
Control signal oscillation filtering circuits, delay locked loops, clock synchronization methods and devices and systems incorporating the control signal oscillation filtering circuits are...
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8134878 |
Signal calibration for memory interface
A method of calibrating memory controller signals within an integrated circuit (IC) can include determining an internal delay of a clock network of the IC and generating a calibrated clock signal...
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RE43223 |
Dynamic memory management
In a method, system and apparatus for management of dynamic memory in battery-powered devices, information is stored in dynamic memory, such as SDRAM chips. Chip partitioning minimizes the number...
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8125251 |
Semiconductor memory device having a clock alignment training circuit and method for operating the same
A semiconductor device includes a clock input block to receive a system clock and a data clock, a clock frequency dividing block to generate a plurality of multi-phase data frequency division...
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8127152 |
Method of operation of a memory device and system including initialization at a first frequency and operation at a second frequency and a power down exit mode
Methods of operation of a memory device and system are provided in embodiments. Initialization operations are conducted at a first frequency of operation during an initialization sequence. Memory...
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8125841 |
Apparatus for generating output data strobe signal
An apparatus for generating an output data strobe signal include a timing control unit configured to detect a specific data pattern and to generate a plurality of timing control signals...
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8122275 |
Write-leveling implementation in programmable logic devices
Circuits, methods, and apparatus for memory interfaces that compensate for skew between a clock signal and DQ/DQS signals that may be caused by a fly-by routing topology. The skew is compensated by...
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8120978 |
Semiconductor memory device having auto-precharge function
To provide a semiconductor memory device including: a first clock generation circuit and a second clock generation circuit that generate a first internal clock and a second internal clock,...
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8122218 |
Semiconductor memory asynchronous pipeline
An asynchronously pipelined SDRAM has separate pipeline stages that are controlled by asynchronous signals. Rather than using a clock signal to synchronize data at each stage, an asynchronous...
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8116161 |
System and method for refreshing a DRAM device
The present invention provides a system and method for refreshing a DRAM device without interrupting or inhibiting read and write operations of the DRAM device. The system may includes refresh...
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8115524 |
Semiconductor device having auto clock alignment training mode circuit
A semiconductor device for applying an auto clock alignment training mode to reduce the time required for a clock alignment training operation. The semiconductor device adjusts the entry time of...
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8111580 |
Multi-phase duty-cycle corrected clock signal generator and memory having same
Memories, multi-phase clock signal generators, and methods for generating multi-phase duty cycle corrected clock signals are disclosed. For example, one such clock signal generator includes a...
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8107314 |
Semiconductor storage device and method for producing semiconductor storage device
A semiconductor storage device comprises a timing control circuit that generates a signal for controlling at least one of a read operation and a write operation; an input-signal pad; a plurality of...
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8107304 |
Distributed write data drivers for burst access memories
An address strobe latches a first address. A burst cycle increments the address internally with additional address strobes. A new memory address is only required at the beginning of each burst...
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8107315 |
Double data rate memory device having data selection circuit and data paths
A double data rate memory device comprises first and second sense amplifiers, a data selection circuit, and a data processing circuit. The first sense amplifier is configured to provide even data...
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8102728 |
Cache optimizations using multiple threshold voltage transistors
In one embodiment, a memory circuit includes one or more memory cells that include transistors having a first nominal threshold voltage, and interface circuitry such as word line drivers and bit...
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8102704 |
Method of preventing coupling noises for a non-volatile semiconductor memory device
Disclosed is a method of preventing coupling noises for a non-volatile semiconductor memory device. According to the method, if an edge of a write operation signal overlaps an activated period of a...
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8102710 |
System and method for setting access and modification for synchronous serial interface NAND
The invention includes a system and method of modifying a setting of a NAND flash memory device using serial peripheral interface (SPI) communication from a master to the NAND flash memory device....
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