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8130550 Memory with sub-blocks  
A non-volatile memory comprising a NOR block with a first sub-block independently addressable from a second sub-block, the two sub-blocks sharing a physical substrate of the NOR block, and a first...
8027209 Continuous programming of non-volatile memory  
A non-volatile storage system connects a signal driver to a first control line that is connected to a first non-volatile storage element, charges the first control line using the signal driver...
8004901 Semiconductor device and method for controlling  
A semiconductor device is disclosed. The semiconductor device includes a plurality of memory cells that are provided in a matrix and that have a charge storage layer made of an insulating film that...
8000158 Semiconductor memory device including repair redundancy memory cell arrays  
A semiconductor memory device includes a plurality of memory cell matrixes each of which contains plural memory cell arrays whose number is lager than 2n and smaller than 2n+1, n being a natural...
7974138 Semiconductor memory device  
A semiconductor memory device includes a selector line selection circuit for selecting, in a read operation, a selector line for connecting a first main bit line connected to the sense amplifier...
7852705 Method of and circuit for configuring a plurality of memory elements  
A method of configuring a plurality of memory elements having selectable dimensions, the method comprising the steps of selecting a width of a data word to be output by a circuit having the...
7729152 Pin configuration changing circuit, base chip and system in package including the same  
A pin configuration changing circuit of a base chip includes pin configuration changing register (PCCR) and a pin configuration changing logic unit (PCCLU). The PCCR stores and provides a pin...
7715271 Using dedicated read output path to reduce unregistered read access time for a FPGA embedded memory  
A memory unit includes width decoding logic enabling data to be accessed in a memory array at different data widths. To improve memory access speed, the memory unit also includes dedicated read...
7715254 Data output circuit of semiconductor memory apparatus and method of controlling the same  
The data output circuit for a semiconductor memory apparatus includes a first control signal generating unit configured to generate a first control signal according to a row address and a read...
7692952 Nanoscale wire coding for stochastic assembly  
Methods for obtaining codes to be implemented in coding nanoscale wires are described. The methods show how to code a reduced number of nanoscale wires through the use of rotation group codes. The...
7599218 Phase change memory comprising a low-voltage column decoder  
An integrated circuit includes a non-volatile memory having memory cells, a memory cell selection circuit having selection blocks, a first device supplying a first voltage applicable to memory...
7489583 Constant-weight-code-based addressing of nanoscale and mixed microscale/nanoscale arrays  
Various embodiments of the present invention include methods for determining nanowire addressing schemes and include microscale/nanoscale electronic devices that incorporate the nanowire addressing...
7414916 Using dedicated read output path to reduce unregistered read access time for FPGA embedded memory  
A memory unit includes width decoding logic enabling data to be accessed in a memory array at different data widths. To improve memory access speed, the memory unit also includes dedicated read...
7388802 Memory protected against attacks by error injection in memory cells selection signals  
A memory comprises memory cells arranged in a memory array, and an address decoder to apply memory cells selection signals to the memory array according to a read address applied to the memory. The...
7106639 Defect management enabled PIRM and method  
A defect management enabled PIRM including a data storage medium providing a plurality of cross point data storage arrays. Each array provides a plurality of memory cells. The arrays are allocated...
7003622 Semiconductor memory  
A semiconductor memory includes a redundant RAM disposed independently of at least one regular RAM, the redundant RAM having redundant memory elements by which defective memory elements of the...
6975553 Nonaligned access to random access memory  
Memory apparatus including a byte-bank organized in N rows and 8 columns, having a capacity of log2(N) bytes, a log2(N) bit address bus operative to address the byte-bank, an address offset bus...
6839266 Memory module with offset data lines and bit line swizzle configuration  
A memory module includes an array of N memory devices, each memory device having M data pins, where N is greater than M, and M and N are positive integers; and N bit lines traversing the array of N...
6768663 Semiconductor device array having dense memory cell array and hierarchical bit line scheme  
A semiconductor device architecture (200) is disclosed. Like unit circuits (202), arranged in rows and columns, are coupled to lower conductive segments (204a-204h). The lower conductive segments...
6667894 Acquisition process by analog signal sampling, and an acquisition system to implement such a process  
An acquisition process for signal sampling includes high-speed analog signal sampling, storing the samples of the analog signal in a matrix of memory cells, and re-reading the samples from the...
6567340 Memory storage cell based array of counters  
A multi-counter based system having a counter array. Each counter of the array having a memory cell. The system also includes an address decoder coupled to the counter array to select at least one...
6507534 Column decoder circuit for page reading of a semiconductor memory  
A column decoder circuit for page reading of a semiconductor memory includes a first level decoder stage, a second level decoder stage, and a plurality of bit selection stages, each comprising a...
6473339 Redundancy architecture for an interleaved memory  
A redundancy architecture for a memory includes an array of memory cells divided into at least a pair of semi-arrays that are singularly addressable. Each semi-array is organized into rows and...
6434433 External components for a microprocessor system for control of plural control elements and operating method  
The external intelligent component (3) connected with a microprocessor system (2) is described for essentially automatic control of a control element (1) without burdening the microprocessor system...
6400597 Semiconductor memory device  
The number of apparently independently operating memory sets can be changed by providing the same number of address setting circuits as that of memory cell arrays. Since the number of mounted...
6373770 Integrated circuit memory devices with configurable block decoder circuits  
A memory device includes a memory array and a configurable decoder circuit operatively associated with the memory array and configurable to one of a first state or a second state. In the first...
6363026 Address generating device for use in multi-stage channel interleaver/deinterleaver  
An address generating device for addressing data stored in an interleaver memory in B rows and F columns, where F is not 2k for a positive integer k. A row counter being responsive to B clock...
6262925 Semiconductor memory device with improved error correction  
When a cell of a memory cell array (C0 and C1) located at a position further from the word select line driver is selected, data that is read from the memory cell array (C0, C1) is sent via only...
6212121 Semiconductor memory device with multiple sub-arrays of different sizes  
A semiconductor memory device includes a memory cell array divided into a plurality of sub-arrays. The number of memory cells per bit line in at least one of the sub-arrays differs from the number...
6192000 Semiconductor memory device having decreased layout area and method of manufacturing the same  
A word line driving circuit drives four word lines in response to a signal supplied from a main row decoder through a main word line and in response to a word line driving voltage supplied from a...
6115305 Method and apparatus for testing a video display chip  
A video chip includes test circuitry for detecting opens and shorts. The circuitry includes a series-connected chain of transistors and a test register. There is a circuit for the column lines and...
5963498 Method for controlling memory address of digital signal processor  
Disclosed is a method for controlling a memory address of a digital signal processor in which a memory address is independently managed for each for during parallel processing of a plurality of...
5943693 Algorithmic array mapping to decrease defect sensitivity of memory devices  
A method and apparatus for addressing a memory device are described. A first logical address is translated into a first physical address to access a first storage location at a first row and a...
5930790 String-match array for substitutional compression  
A circuit for implementing a substitutional compressor. Comparators compare a current input pixel against a large number of previous pixels, the "history", stored in a series of shift registers....
5659503 Nonvolatile semiconductor memory having an improved reference voltage generating circuit  
In a nonvolatile semiconductor memory, in addition to a first voltage generating circuit for supplying various voltages to memory cell transistors in various operations, there is provided a second...
5572481 Efficient local-bus ROM memory for microprocessor systems  
An efficient technique or providing ROM memory on a microprocessor local bus is described whereby a ROM and all necessary address decoding and control circuitry is incorporated in a single...
5515329 Variable-size first in first out memory with data manipulation capabilities  
A FIFO memory system exhibits data processing capabilities by the inclusion therein of a digital signal processor and an associated dynamic random access memory. The digital signal processor...
5506813 Semiconductor apparatus and method of manufacturing the same  
In a semiconductor memory apparatus having a cell array structure wherein occurrence of leak current is reduced and a margin at the time of sensing is increased, a plurality of memory transistors...
5500814 Memory system and cache memory system  
A memory system, wherein the respective byte memories 1 to 4 is configured so that data of word unit which are the targets of the parity calculation done by the parity calculation circuits 5 to 8...
5467319 CAM array and method of laying out the same  
A data compressor generates codewords representative of the location and length of a string match between an input data stream and a CAM array vocabulary table. A data decompressor looks up the...
5440521 Semiconductor integrated circuit device  
A semiconductor integrated circuit device constituted by a plurality of sets each of which having a pair of memory mats and each memory mat having a plurality of memory cells arranged in a matrix...
5440523 Multiple-port shared memory interface and associated method  
A multi-port shared memory system is provided which includes multiple ports for transfering data; a plurality of memory access buffers; and an interconnection matrix circuit for distributing...
5327389 Semiconductor memory device having a block selection function with low power consumptions  
A semiconductor memory device divided into a number of main blocks each main block having a number of subblocks selects a single main block and enables the subblocks of the selected main block, so...
5313431 Multiport semiconductor memory device  
A multiport memory device includes first and second memory cell arrays divided by a shared sense amplifier circuit, a first serial data register capable of transferring data with a row in the first...
5287322 Integrated circuit dual-port memory device having reduced capacitance  
A dual-port memory device provides for a memory array which is divided approximately in half. Between the two halves of the array, a bit line crossover scheme is provided which minimizes stray...
5103426 Decoding circuit and method for functional block selection  
An address decoding circuit for a functional block comprises branch portions serially connected with each other, in which a selecting signal is outputted on one of two output portions in accordance...
5058068 Redundancy circuit with memorization of output contact pad position  
The disclosure concerns integrated memories and their redundancy circuits. The described redundancy concerns the memories organized in k groups of p columns (for example k=8 and p=64) to give words...
RE33676 Gate array circuit for decoding circuits  
A decoder circuit for decoding different combinations of supplied original input address bits, comprising at least one predecode circuit responsive to the original input address bits for producing...
5040153 Addressing multiple types of memory devices  
The present invention provides a memory addressing system that can accommodate multiple size DRAMS. DRAMS of various sizes can be mixed in a variety of ways. The present invention provides a...
4972380 Decoding circuit for functional block  
An address decoding circuit for a functional block comprises branch portions serially connected with each other, in which a selecting signal is outputted on one of two output portions in accordance...
Matches 1 - 50 out of 107 1 2 3 >