|
Match
|
Document |
Document Title |
|
|
7567453 |
Advanced multi-bit magnetic random access memory device
An advanced multi-bit magnetic random access memory device and a method for writing to the advanced multi-bit magnetic random access memory device. The magnetic memory includes one or more...
|
|
|
7518919 |
Flash memory data correction and scrub techniques
In order to maintain the integrity of data stored in a flash memory that are susceptible to being disturbed by operations in adjacent regions of the memory, disturb events cause the data to be...
|
|
|
7477567 |
Memory storage device with heating element
A memory storage device is provided that includes a storage cell having a changeable magnetic region. The changeable magnetic region includes a material having a magnetization state that is...
|
|
|
7345945 |
Line driver circuit for a semiconductor memory device
A semiconductor memory device having a word line driver circuit configured in stages. A plurality of sub word line driver circuits are connected, in parallel, to each main word line, and provide a...
|
|
|
7196955 |
Hardmasks for providing thermally assisted switching of magnetic memory elements
An exemplary magnetic random access memory comprises a plurality of hardmasks, a plurality of magnetic memory elements each having been formed using a corresponding one of the hardmasks, and at...
|
|
|
7158397 |
Line drivers that fits within a specified line pitch
Line drivers that fit within a specified line pitch. One method of placing line drivers completely underneath a cross point array requires splitting the line driver up so that a portion of the line...
|
|
|
7072207 |
Thin film magnetic memory device for writing data of a plurality of bits in parallel
For writing K-bit write data in parallel (K is integer at least 2), bit lines each arranged for each memory cell columns and at least K current return lines are provided. K selected bit lines to...
|
|
|
7003622 |
Semiconductor memory
A semiconductor memory includes a redundant RAM disposed independently of at least one regular RAM, the redundant RAM having redundant memory elements by which defective memory elements of the...
|
|
|
6975555 |
Magnetic random access memory using memory cells with rotated magnetic storage elements
A magnetic random access memory circuit comprises a plurality of magnetic memory cells, each of the memory cells including a magnetic storage element having an easy axis and a hard axis associated...
|
|
|
6950369 |
Magnetic memory device capable of passing bidirectional currents through the bit lines
A plurality of word lines (WL 1 ) are provided in parallel to one another and a plurality of bit lines (BL 1 ) are provided in parallel to one another, intersecting the word lines (WL 1 )...
|
|
|
6903982 |
Bit line segmenting in random access memories
An integrated memory circuit and corresponding method for segmenting bit lines are provided, where the integrated memory circuit includes a sense amplifier, a layered bit line in signal...
|
|
|
6842831 |
Low latency buffer control system and method
A memory controller (MC) includes a buffer control circuit (BCC) to enable/disable buffer coupled to a terminated bus. The BCC can detect transactions and speculatively enable the buffers before...
|
|
|
6807112 |
Mask programmable read only memory
In view of the transistor off leakage increasing with device miniaturization, the invention provides a semiconductor integrated circuit capable of high-speed readout by eliminating the need for a...
|
|
|
6778432 |
Thin film magnetic memory device capable of stably writing/reading data and method of fabricating the same
A thin film magnetic memory device includes a plurality of program cells each storing program data constituting information on a bit unit basis, each program cell having a magnetic storing part...
|
|
|
6778445 |
Pipeline nonvolatile memory device with multi-bit parallel read and write suitable for cache memory.
Peripheral circuitry writes/reads input data and output data of L bits (L: integer of at least 2) that is input/output to/from a data node into/from first and second memory cell blocks that are...
|
|
|
6762952 |
Minimizing errors in a magnetoresistive solid-state storage device
Exemplar embodiments are disclosed which allow errors in a magnetoresistive solid-state storage device, such as a magnetic random access memory (MRAM) device, to be minimized. An illustrative...
|
|
|
6750540 |
Magnetic random access memory using schottky diode
A magnetic random access memory (MRAM) using a Schottky diode is disclosed. In order to achieve high integration of the memory device, a word line is formed on a semiconductor substrate without...
|
|
|
6674663 |
Nonvolatile storage device and operating method thereof
A nonvolatile storage device and method of operation capable of preventing opens in a word line and/or bit line that may result from electromigration is disclosed. A nonvolatile storage device...
|
|
|
6667899 |
Magnetic memory and method of bi-directional write current programming
A magnetic memory ( 400 ) is programmed by selectively conducting current in opposite directions in both word and bit lines to reduce electromigration effects in word lines and bit lines. Various...
|
|
|
6639823 |
Ferroelectric memory device and method of driving the same
A ferroelectric memory device includes a memory cell array in which a plurality of memory cells having at least one ferroelectric capacitor are arranged. Three or more values of data (Pr( 0 ), P 1...
|
|
|
6618317 |
Write system architecture of magnetic memory array divided into a plurality of memory blocks
During data write, a first driver electrically connects a fist shared node to one of first and second voltages in accordance with write data. A second driver electrically connects a second shared...
|
|
|
6541792 |
Memory device having dual tunnel junction memory cells
A memory device includes memory cells having two tunnel junctions in series. In order to program a selected memory cell, a first tunnel junction in the selected memory cell is blown. Blowing the...
|
|
|
6317359 |
Non-volatile magnetic circuit
A device and method for sensing the status of a non-volatile magnetic latch. A cross-coupled inverter pair latch cell is employed for the data sensing. During the `Sense` cycles, the inputs to the...
|
|
|
6199025 |
Semiconductor device having selectable device type and methods of testing device operation
A semiconductor device includes a device-type switching circuit which determines selection signals A based on fuse-cut conditions in a first mode, and determines selection signals based on control...
|
|
|
5793697 |
Read circuit for magnetic memory array using magnetic tunnel junction devices
A sensing circuit reads the magnetic state of individual memory cells making up a nonvolatile magnetic random access memory (MRAM) array. Each memory cell is a magnetic tunnel junction (MTJ)...
|
|
|
5579267 |
Semiconductor pipeline memory device eliminating time loss due to difference between pipeline stages from data access
A semiconductor pipeline memory device has a controller for producing first, second and third timing clock signals for transferring a column address and a read-out data bit through first, second...
|
|
|
5546348 |
Semiconductor disc storage
A semiconductor storage device is connected to at least one magnetic storage device. The input and output of data is made between the semiconductor storage device and an information processing...
|
|
|
3846769 |
MAGNETIC DATA STORAGE ARRANGEMENT HAVING SEQUENTIAL ADDRESSING OF ROWS
A magnetic data storage arrangement of the kind including a plurality of current operated bistable magnetic elements arranged in rows and columns such that a data word may be stored in a selected...
|
|
|
3774181 |
CURRENT DRIVER SYSTEM FOR A CORE MEMORY
A system for supplying a current to a core memory stack having substantial inductance including a transformer having a selectively variable primary/secondary turns ratio. The variable turns ratio...
|
|
|
3680048 |
CORE DRIVE AND BIASING SYSTEM
A read/write drive circuit for a circuit having a driver and a plurality of read/write circuit units connected in parallel thereto, wherein when one desired circuit unit is driven with a potential...
|
|
|
3675221 |
MAGNETIC CORE MEMORY LINE SINK VOLTAGE STABILIZATION SYSTEM
A magnetic core memory line sink voltage stabilization system is disclosed using a current or voltage source to charge a group of selected lines. The sink ends through which the lines are charged...
|
|
|
3671949 |
METHOD AND APPARATUS FOR DRIVING MEMORY CORE SELECTION LINES
Apparatus for supplying selection lines of a magnetic core memory with drive currents of uniform amplitude and configuration. The apparatus includes a pair of line selection switches at opposite...
|
|
|
3621371 |
CURRENT PULSE STABILIZER FOR VARIABLE LOADS
Amplitude of a fast-rise pulse current is stabilized under varying load conditions by a transformer having a first winding connected in series between a pulse voltage source and a variable load. A...
|
|
|
3603938 |
DRIVE SYSTEM FOR A MEMORY ARRAY
A drive system for a magnetic core array is disclosed which employs transistor switches for selectively applying the energizing currents to the drive lines. The transistor switches are in the form...
|
|
|
3587065 |
CIRCUIT ARRANGEMENT FOR GENERATING STEEP FLANKED PULSES TO A MAGNETIC MEMORY
A circuit arrangement for generating current impulses with very steep flanks, utilizing a current superimposed on that of a current impulse source connected to a time-dependently controlled voltage...
|
|
|
3587064 |
SELECTION CIRCUIT FOR MEMORY LINES
A selection circuit is disclosed for selectively sending pulses of opposite polarity to a two-terminal load element selected from a multiplicity of such elements and which circuit is particularly...
|
|
|
3579209 |
HIGH SPEED CORE MEMORY SYSTEM
A magnetic core memory system is disclosed comprising a rectangular array of magnetic cores. A first plurality of independent wires thread cores along one axis and a second plurality of dependent...
|
|
|
3568173 |
MEMORY STROAGE ELEMENT DRIVE CIRCUIT
A memory core wire drive circuit is disclosed in which one wire end is normally biased to ground but controlled through a pair of transistors each connecting through series resistors to sources of...
|
|
|
3551904 |
MEMORY SYSTEM
|
|
|
3550100 |
INFORMATION STORAGE CONTROL APPARATUS FOR A MAGNETIC CORE MEMORY
|
|
|
3544978 |
METHOD AND APPARATUS FOR DRIVING MEMORY CORE SELECTION LINES
|
|
|
3537081 |
ARRANGEMENT FOR ATTENUATION OF THE OVERSHOOT OF CURRENT PULSES IN CORE MEMORIES
|
|
|
3532816 |
TRANSDUCER DRIVER CIRCUIT CONTROLLED BY SATURATING CORES
|
|
|
3524174 |
SEARCH MEMORY
|
|
|
3500351 |
MAGNETIC RECORDING MEMORY
|
|
|
3488643 |
NON-RETURN TO ZERO DRIVING METHOD FOR MAGNETIC MEMORY DEVICES
|
|
|
3488641 |
COINCIDENT CURRENT READ ONLY MEMORY USING LINEAR MAGNETIC ELEMENTS
|
|
|
3487383 |
COINCIDENT CURRENT DESTRUCTIVE READ-OUT MAGNETIC MEMORY SYSTEM
|
|
|
3479656 |
COINCIDENT CURRENT MEMORY APPARATUS AND METHOD
|
|
|
3474419 |
WORD DRIVE SYSTEM FOR A MAGNETIC CORE MEMORY
|