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7391669 Semiconductor memory device and core layout thereof  
A semiconductor memory device of one aspect includes a memory cell block including n global word lines, and corresponding m sub word lines for each of the n global word lines, where n and m are...
7391660 Address path circuit with row redundant scheme  
An address path circuit with a row redundant scheme may include an address buffer for buffering an external address to output an internal address, a command buffer for buffering a plurality of...
7391657 Semiconductor memory chip  
A semiconductor memory chip includes: a reception interface section for receiving external data, command, and address signals in form of serial signal frames; an intermediate data buffer for...
7388804 Semiconductor memory device for driving a word line  
A semiconductor memory device for driving a word line is provided. The enabling timing of a word line is advanced using a block information signal that contains no redundancy information, thereby...
7388794 Individual I/O modulation in memory devices  
A DRAM circuit with reduced power consumption and in some circumstances faster memory array access speed. Input/output lines connected to a memory array are sensed according to their...
7385871 Apparatus for memory device wordline  
A method and apparatus for improving the speed of a wordline in a memory device. A wordline structure includes a main wordline for selectively distributing a main wordline signal and a plurality of...
7385849 Semiconductor integrated circuit device  
A semiconductor integrated circuit device is disclosed. The device includes a memory cell array, an I/O buffer, a read/write buffer, an error checking and correcting circuit, and an initialization...
7385838 Semiconductor device with a non-erasable memory and/or a nonvolatile memory  
A semiconductor device comprises a plurality of memory cells, a central processing unit, a timer circuit which times a RESET time, and a timer circuit which times a SET time. A threshold voltage of...
7379380 Low power multi-chip semiconductor memory device and chip enable method thereof  
A multi-chip semiconductor device capable of selectively activating and deactivating the individual semiconductor chips of the device and a chip enable method thereof are provided. The individual...
7379378 Over driving control signal generator in semiconductor memory device  
A bit line over driving control signal generator generates an over driving control signal in response to an over driving signal. The over driving signal is generated in response to an active...
7379377 Memory array decoder  
An apparatus and method for selecting a storage location in a memory device including receiving at least one of a pre-decoded location address signal, a match signal, and a redundant location...
7379376 Internal address generator  
An internal address generator includes a plurality of column address generators, a mode column address generator, and a drive clock generator. Each column generator receives a corresponding...
7379375 Memory circuits having different word line driving circuit configurations along a common global word line and methods for designing such circuits  
Memory circuits having different configurations of local word line driving circuits (LWLDC) and methods for designing such circuits are provided. The memory circuits include an array of memory...
7379370 Semiconductor memory  
After a refresh operation, a word control circuit holds the selection state of a word line selection signal line selected in each memory block corresponding to a refresh address. Further, in...
7379367 Memory controller and semiconductor comprising the same  
A memory controller and a semiconductor device comprising the same are provided. The semiconductor device comprises a memory block comprising a plurality of memory banks and a memory controller....
7379351 Non-volatile semiconductor memory and programming method  
In one aspect, a programming method is provided for a non-volatile semiconductor memory device which includes a plurality of electrically programmable and erasable memory cells, and transmission...
7376038 Fast access memory architecture  
A computer system including a control logic and a storage coupled to the control logic. The storage includes a plurality of bitcells and bitlines used to transfer data between the control logic and...
7376035 Semiconductor memory device for performing refresh operation and refresh method thereof  
A semiconductor memory device for performing a refresh operation comprises a memory cell array, a driving control unit, a word line driving unit, a sense amplifier driving unit and a sense...
7376034 Parallel data storage system  
A parallel data storage system for storing data received from, or retrieving data to, a host system using multiple data storage devices. The system includes an interface for communicating with the...
7372767 Nonvolatile semiconductor memory device having multi-level memory cells and page buffer used therefor  
A non-volatile semiconductor memory device includes a memory array having nonvolatile memory cells. The memory device also includes a page buffer coupled to the memory array through first and...
7372766 Semiconductor memory device  
A semiconductor memory device may include a switching unit to selectively connect a bitline pair and a pair of input/output lines in response to a column selection line signal; a column selection...
7372765 Power-gating system and method for integrated circuit devices  
A power-gating system and method for integrated circuit devices wherein the minimization of “Standby” or “Sleep Mode” current is a design factor and wherein an output stage is coupled...
7372756 Non-skipping auto-refresh in a DRAM  
In a dynamic random access memory device, an auto-refresh method comprises receiving a command for the memory device to operate in a half-density mode. This causes a remapping circuit to remap a...
7372728 Magnetic random access memory array having bit/word lines for shared write select and read operations  
A random access memory array includes random access memory elements arranged in a rows and columns. The elements of each row have a word line and a write digit line and the elements of each column...
7369454 Semiconductor integrated circuit device  
A semiconductor integrated circuit device comprises several blocks including a word line connected with a memory cell, a row decoder selecting the word line, and a block decoder selecting the...
7369445 Methods of operating memory systems including memory devices set to different operating modes and related systems  
A method of operating a memory system including a plurality of memory devices coupled to a command address bus may be provided. In particular, a first memory device of the plurality of memory...
7366822 Semiconductor memory device capable of reading and writing data at the same time  
A semiconductor memory device includes a plurality of banks. A data path may be divided into a read data path and a write data path, therefore, parallel processing of write and read commands are...
7366051 Word line driver circuitry and methods for using the same  
Word line driver circuitry for selectively charging and discharging one or more word lines is provided. The driver circuitry uses a dual transistor topology, where a first transistor is driven by a...
7359280 Layout structure for sub word line drivers and method thereof  
A layout structure for sub word line drivers and method thereof. The example layout structure may include at least one N-channel transistor arrangement having a cross sectional width and a cross...
7359279 Integrated circuit memory array configuration including decoding compatibility with partial implementation of multiple memory layers  
An integrated circuit having a three-dimensional memory array provides for a given number of memory planes, but may be fabricated instead to include a lesser number of memory planes by omitting the...
7359278 Method for producing an integrated memory module  
A method for producing an integrated memory module containing a command decoding device that responds to external operation commands to set operating states of the memory module for carrying out...
7359277 High speed power-gating technique for integrated circuit devices incorporating a sleep mode of operation  
A high speed power-gating technique for an integrated circuit device having a Sleep Mode of operation comprises providing an output stage coupled between a supply voltage source and a reference...
7359273 Semiconductor memory device having layout for minimizing area of sense amplifier region and word line driver region  
A semiconductor memory device has a layout that minimizes the area required for sense amplifier and word line driver regions. In the semiconductor memory device of the present invention, decoding...
7359265 Data flow scheme for low power DRAM  
Circuits and methods to minimize power required for sensing and precharge of DRAMs have been achieved. A control circuit ensures that during READ operations the duration of sensing of DRAM cell and...
7359261 Memory repair system and method  
An IC includes a memory module that stores at least one of data and code. A memory repair database stores data relating to defective memory addresses. A memory control module communicates with the...
7359258 Semiconductor memory with wordline timing  
A semiconductor memory with wordline timing, which links activating a wordline to an isolation signal. The isolation signal is applied to a memory section adjacent the memory section containing the...
7359254 Controller for controlling a source current to a memory cell, processing system and methods for use therewith  
A controller for controlling a source current of a memory cell for use in a static random access memory (SRAM) includes a bias generator for supplying a bias current to the memory cell. A read...
7359242 Semiconductor memory device with small number of repair signal transmission lines  
In an embodiment, a semiconductor memory device has a small number of repair signal transmission lines. The semiconductor memory device includes m repair redundancy blocks, each including n repair...
7359228 Semiconductor memory device capable of realizing a chip with high operation reliability and high yield  
A semiconductor memory device capable of preventing a defect caused by lowering the etching precision in an end area of the memory cell array is provided. A first block is constructed by first...
7355915 Memory circuit with supply voltage flexibility and supply voltage adapted performance  
The inventive memory circuit comprises a plurality of memory cells. The memory circuit further comprises a memory access means being controlled by at least one control signal. In addition, a...
7355908 Nonvolatile storage device and self-redundancy method for the same  
The nonvolatile storage device is made up of a memory array divided into a plurality of data-storage units and a plurality of redundancy-storage units for replacing respective failed data-storage...
7352647 Reduced power usage in a memory for a programmable logic device  
A method and system to reduce power usage of memory within a programmable logic device (PLD) is disclosed. In one embodiment, a memory block is formed from a plurality of memory sub-blocks. A data...
7352644 Semiconductor memory with reset function  
A synchronous dynamic random access memory (SDRAM) integrated circuit (IC) configured to receive an external Reset signal for resetting the IC includes an input buffer configured to generate a...
7352619 Electronic memory with binary storage elements  
An electronic memory using true and complementary dual bit lines and dual binary storage elements cell architecture comprising a memory cell pair with four binary storage elements with each memory...
7352609 Voltage controlled static random access memory  
A static random access memory (SRAM) ( 200, 400 ) comprising a plurality of SRAM cells ( 204 ), a plurality of wordlines (WL 0 -WLN) and a voltage regulator ( 240, 240′, 300, 516 ) for driving...
7352604 Memory and driving method of the same  
According to the invention, mounting area is decreased and yield is improved by decreasing the number of elements, and a memory with less burden on peripheral circuitry and a driving method thereof...
7349288 Ultra high-speed Nor-type LSDL/Domino combined address decoder  
An ultra high speed address decoder uses a combination of Domino logic circuits and LSDL logic circuits. N address bits are converted into N logic true address bits and N complementary address...
7349287 Address decoder, storage device, processor device, and address decoding method for the storage device  
The address decoder includes: a plurality of decode units each formed by a combinational logic circuit; an inverting circuit which inverts an output of said decode unit; an AND circuit which...
7349286 Memory component and addressing of memory cells  
A memory component comprises a plurality of memory cells that are each assigned an address, and an address memory for storing numerical values which are uniquely related to addresses of defective...
7349272 Multi-port semiconductor memory device  
A semiconductor memory device includes: a plurality of ports configured to perform a serial input/output (I/O) data communication with external devices; a plurality of banks configured to perform a...
Matches 1 - 50 out of 3209 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >