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8184498 Semiconductor memory device  
A semiconductor memory device includes a row control circuit block and a column control circuit block each performing an access control over a memory cell array, a data I/O circuit block...
8184500 Semiconductor memory device and method for operating the same  
A semiconductor memory device includes a plurality of banks, a first bank selection driving control signal generation unit configured to generate a plurality of first bank selection driving control...
8184494 Cell inferiority test circuit  
A cell inferiority test circuit includes a compression data generator configured to compress selected data in response to selection signals and to generate compression data including information...
8179739 Semiconductor device and its manufacturing method  
A technique capable of manufacturing a semiconductor device without posing contamination in a manufacturing apparatus regarding a phase change memory including a memory cell array formed of memory...
8179737 Semiconductor memory apparatus  
A semiconductor memory apparatus includes an internal circuit configured to be driven by current flowing between first and second voltage nodes, and a current control unit configured to control an...
8179719 Systems and methods for improving error distributions in multi-level cell memory systems  
A memory system includes a state set module that provides a first state set having a plurality of states, each being assigned to represent a particular data sequence, and a second state set having...
8174924 Power saving method and circuit thereof for a semiconductor memory  
A power saving method for a semiconductor memory is provided. The power saving method for a semiconductor memory including the steps of receiving a plurality of address codes, each of which has a...
8174878 Nonvolatile memory, memory system, and method of driving  
Provided are a nonvolatile memory and related method of programming same. The nonvolatile memory includes a memory cell array with a plurality of nonvolatile memory cells and a write circuit. The...
8174916 Bit line precharge circuit and a semiconductor memory apparatus using the same  
A bit line precharge circuit includes a precharge signal generation unit configured to generate first and second precharge signals that are enabled at different timing points by receiving a bit...
8169837 Semiconductor memory device and method for generating bit line equalizing signal  
A bit line equalizing signal generator of a semiconductor memory device uses a supply voltage and a pumping voltage in stages during a period where a bit line equalizing signal is enabled, thereby...
8171258 Address generation unit with pseudo sum to accelerate load/store operations  
In an embodiment, an address generation unit (AGU) is configured to generate a pseudo sum from an index portion of two or more operands. The pseudo sum may equal the index if the carry-in of the...
8169847 Semiconductor memory apparatus and refresh control method of the same  
A semiconductor memory apparatus and refresh control method are presented. The semiconductor memory apparatus includes a memory cell block composed of a multiplicity of floating body cell (FBC)...
8164973 Storage apparatus and method of controlling storage apparatus  
A storage apparatus includes: a plurality of storage sections each of which corresponds to each of a plurality of addresses; a read pointer register that outputs a read pointer indicating an...
8164971 Dual power rail word line driver and dual power rail word line driver array  
A dual power rail word line driver for driving a word line of a memory array according to a predecode signal from a decoder powered by a first supply voltage is provided. A signal buffering unit is...
8159896 Local power domains for memory sections of an array of memory  
Memories, memory arrays, and methods for selectively providing electrical power to memory sections of a memory array are disclosed. A memory array can be operated by decoupling row decoder...
8159887 Clock synchronization in a memory system  
A system and method for synchronizing a strobed memory system 10. During memory read and/or memory write operations the corresponding data strobe is sampled at the data destination 50/55 according...
8159898 Architecture of highly integrated semiconductor memory device  
A semiconductor memory device includes: a first row control circuit region corresponding to a first memory bank; a first column control circuit region corresponding to the first memory bank; a...
8159899 Wordline driver for memory  
Subject matter disclosed herein relates to accessing memory, and more particularly to a wordline driver of same.
8154946 Data storage device  
A device to selectively activate memory chips includes a memory unit including n memory chips activated in response to n memory chip activation signals (n is a natural number), a controller to...
8154912 Volatile memory elements with soft error upset immunity  
Memory elements are provided that exhibit immunity to soft error upset events when subjected to high-energy atomic particle strikes. The memory elements may each have ten transistors including two...
8154945 Decoding circuit withstanding high voltage via low-voltage MOS transistor and the implementing method thereof  
The present invention discloses a decoding circuit withstanding high voltage via a low-voltage MOS transistor, where negative high voltage that can be withstood can be as high as double what the...
8156291 Memory register encoding systems and methods  
Apparatus, systems, and methods are disclosed that operate to encode register bits to generate encoded bits such that, for pairs of addresses, an encoded bit to be coupled to a first address in a...
8154947 Multi-column addressing mode memory system including an integrated circuit memory device  
A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit...
8154902 Bit line decoder architecture for NOR-type memory array  
An integrated circuit including a plurality of bit lines, a memory array, and a bit line decoder. The memory array includes a plurality of memory cells, wherein each memory cell is respectively...
8149636 Semiconductor memory device with pulse width determination  
A semiconductor memory device includes a reset signal generating unit configured to generate a reset control signal by delaying a column command signal by an amount of time varying proportional to...
8149626 Threshold voltage digitizer for array of programmable threshold transistors  
A method and system for determining a respective threshold voltage of each of a plurality of transistors in a memory array. The method includes: applying a ramp voltage to gates of the plurality of...
8149637 Semiconductor device capable of being tested after packaging  
Provided is a semiconductor device capable of effectively testing whether memory cells and a memory cell array are defective. The semiconductor device may include a memory cell array having a...
8144497 Self-identifying stacked die semiconductor components  
A semiconductor die having a functional circuit (e.g., a memory array) and a decode circuit suitable for use in a stacked die semiconductor component (e.g., a random access memory component) is...
8144533 Compensatory memory system  
A compensatory memory system is described. This memory system substantially improves performance by adapting an associated delay in a way that optimizes circuit performance.
8144541 Method and apparatus for adjusting and obtaining a reference voltage  
A method for adjusting a reference voltage is provided, including: decoding a default code configured in a reference voltage register in a chip to obtain an actual reference voltage; comparing the...
8144510 Method and system for programming multi-state memory  
In a multi-level memory cell, when data to be programmed arrives, the cell is programmed to the lowest-charge state in which any bit position that is being programmed or has already been programmed...
8144520 Non-volatile memory device and method of reading data in a non-volatile memory device  
A non-volatile memory device includes a row decoder and a memory cell array. The row decoder generates a read voltage, and first, second and third drive voltages. The memory cell array includes a...
8139423 Write driving device  
A write driving device includes a buffer unit, a duration signal generation unit, and a data input clock pulse generation unit. The buffer unit is configured to generate an alignment signal in...
8139426 Dual power scheme in memory circuit  
A semiconductor memory device includes address signal level shifters configured to transform a low level address signal into a higher level address signal. A decoder is configured to receive the...
8139437 Wordline driving circuit of semiconductor memory device  
Wordline driving circuit of semiconductor memory device includes a bias generator configured to generate a threshold bias voltage for accessing data, an over-driver configured to increase the...
8134884 Semiconductor memory device  
A semiconductor memory device comprises a memory unit having a first and a second port and including plural banks; a bank address conversion circuit operative to convert a first bank address fed...
8134867 Memory array having a programmable word length, and method of operating same  
A memory cell array and device having a memory cell array (i.e., an integrated circuit device, for example, a logic device (such as, a microcontroller or microprocessor) or a memory device (such...
8134861 Memory access method and semiconductor memory device  
A semiconductor memory device includes a memory cell array provided with blocks each having a plurality of memory cells arranged in columns and rows, a column selection circuit selecting a column...
8130589 Semiconductor memory device using only single-channel transistor to apply voltage to selected word line  
A semiconductor memory device has a memory cell array, a first transistor of a first conductivity type, a second transistor of a second conductivity type and a third transistor of the first...
8130550 Memory with sub-blocks  
A non-volatile memory comprising a NOR block with a first sub-block independently addressable from a second sub-block, the two sub-blocks sharing a physical substrate of the NOR block, and a first...
8130556 Pair bit line programming to improve boost voltage clamping  
A programming technique reduces program disturb in a set of non-volatile storage elements by programming using selected bit line patterns which increase the clamped boosting potential of an...
8130587 Efficient method of replicate memory data with virtual port solution  
A hardware arrangement for a memory bitcell, including a primary decoder for decoding a common memory address portion among a plurality of memory addresses, and a plurality of secondary decoders...
8130588 Semiconductor memory device having power saving mode  
A semiconductor memory device includes a memory cell array arranged in rows and columns, a row decoder and a control circuit. The row decoder drives word lines connected to the memory cell array by...
8125847 Semiconductor memory device and access method thereof  
Example embodiments provide a semiconductor memory device that may include: a cell array arranged in pluralities of rows and columns; and a sense amplifier conducting writing and reading operations...
8125211 Apparatus and method for testing driver writeability strength on an integrated circuit  
An apparatus and method for testing driver write-ability strength on an integrated circuit includes one or more drive detection units each including a number of drivers. At least some of the...
8125809 Adjustable write bins for multi-level analog memories  
An analog memory having adjustable write bins including a system for writing to the memory. The system includes a write apparatus interpreting one or more write control signals, generating a write...
8120938 Method and apparatus for arranging multiple processors on a semiconductor chip  
A method and apparatus for connecting multiple cores to form a multi core processor. Each processor is connected to at least two other processors, each of which is a mirror image of the first...
8120987 Structure and method for decoding read data-bus with column-steering redundancy  
A random access memory circuit enabling a decodable sense amplifier array for power saving with column steering redundancy. A first decoder receives an input address and accesses at least one...
8120990 Flexible memory operations in NAND flash devices  
A flash memory device having at least two bank, where the each bank has an independently configurable page size and core controller. The core controller is local to each bank, and governs memory...
8120977 Test method for nonvolatile memory device  
A test method for nonvolatile memory devices where, in one aspect of the method, a specific operation mode is selected according to a signal input through a single I/O pin in a period in which a...
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