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RE44230 |
Clock signal generation apparatus for use in semiconductor memory device and its method
A clock signal generation apparatus for generating a reference clock signal for outputting data in synchronization with an external clock signal from a semiconductor memory device, including: a...
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8441887 |
Decoding circuit withstanding high voltage via low-voltage MOS transistor and the implementing method thereof
A decoding circuit withstanding high voltage via a low-voltage MOS transistor, where negative high voltage that can be withstood can be as high as double what the transistor itself can withstand...
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8441870 |
Data strobe signal output driver for a semiconductor memory apparatus
A data strobe signal output driver includes a trigger block, a predriver block, and a main driver block. The trigger block is configured to receive a first signal, a second signal, a first clock...
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8441886 |
System and method for processing signals in high speed DRAM
A method is disclosed for operating a memory device, including providing a timing signal comprising a plurality of clock cycles, providing an activate signal, and providing a bank address signal....
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8441888 |
Write command and write data timing circuit and methods for timing the same
Circuits, memories, and methods for latching a write command and later provided write data including write command and write data timing circuits. One such timing circuit includes internal write...
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8441876 |
Memory module including parallel test apparatus
A memory module including a plurality of ranks. Each of the ranks includes a parallel test apparatus for simultaneous testing and a parallel test control unit. In response to a parallel test mode...
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8441885 |
Methods and apparatus for memory word line driver
A word line driver circuit and corresponding methods are disclosed. An apparatus, comprising a decoder circuit coupled to receive address inputs, and having a decoder output; and a word line clock...
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8441883 |
Memory arrangement for accessing matrices
A memory arrangement is provided having a plurality of memory elements, the elements being associated with a memory space that can be addressed in a row and column fashion during a write or a read...
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8441884 |
Semiconductor memory device, image processing system, and image processing method
A semiconductor memory device comprises: a memory cell group, the memory cell including a number of which is 2n, the n being a positive integer; and a first decoder provided with respect to each of...
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8441852 |
Stacked memory device and method of fabricating same
A stacked semiconductor memory device comprises a semiconductor substrate having a functional circuit, a plurality of memory cell array layers, and at least one connection layer. The memory cell...
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8437205 |
Semiconductor memory apparatus
Various embodiments of a semiconductor memory apparatus are disclosed. In one exemplary embodiment, the semiconductor memory apparatus may include: a column control signal generator configured to...
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8437172 |
Decoders using memristive switches
A decoding structure employs a main terminal (130), a first memristive switch (112) connected between the main terminal (130) and a first addressable terminal (132), and a second memristive switch...
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8437215 |
Memory with word-line segment access
A memory comprises a row of bit cells, including a first plurality of bit cells and a second plurality of bit cells. A first word line segment driver is connected to the first plurality of bits...
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8437163 |
Memory dies, stacked memories, memory devices and methods
Memory die, stacks of memory dies, memory devices and methods, such as those to construct and operate such die, stacks and/or memory devices are provided. One such memory die includes an...
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8437201 |
Word-line level shift circuit
A dual word-line level shifter circuit and associated SRAM. A circuit is disclosed that includes a first transistor gated by a data input at the lower voltage, and a second transistor gated by a...
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8432725 |
Static random access memory structure and control method thereof
A static random access memory (SRAM) is provided. The SRAM structure includes an SRAM array, a word line decoder, and a reference bit line device. The SRAM array comprises at least one SRAM bit...
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8432761 |
Data bus control scheme for and image sensor and image sensor including the same
A memory system including a plurality of memory cells configured to receive digital signals includes an address decoder, a data bus, and a sense amplifier configured to receive data output from...
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8432758 |
Device and method for storing error information of memory
A device for storing error information of a memory device includes a plurality of parent memories and a plurality of child memories. Each of the parent memories stores a row address and a column...
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8432755 |
Random access memory devices having word line drivers therein that support variable-frequency clock signals
Integrated circuit memory devices include an array of memory cells electrically coupled to a plurality of word lines and a word line driver circuit. The word line driver circuit includes a...
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8432762 |
Bitline sense amplifier, memory core including the same and method of sensing charge from a memory cell
A bitline sense amplifier includes a pre-sensing unit and an amplification unit. The pre-sensing unit is connected to a first bitline and a second bitline, and is configured to perform a...
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8432738 |
Apparatus and method for reduced peak power consumption during common operation of multi-nand flash memory devices
System and method for executing a global memory command in a multi-chip non-volatile memory device having a plurality of non-volatile memories. The global memory command is received at each...
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8432766 |
Multi-column addressing mode memory system including an integrated circuit memory device
A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit...
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8432731 |
Magnetically coupled electrostatically shiftable memory device and method
A method, system, and apparatus magnetically coupled electrostatically shiftable memory device and method are disclosed. In one embodiment, a method includes electrostatically decoupling a separate...
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8427898 |
Method and apparatus for performing multi-block access operation in nonvolatile memory device
A nonvolatile memory device comprises a first mat, a second mat, a third mat, a first address decoder, a second address decoder, and a third address decoder. The first mat comprises first memory...
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8427878 |
Non-volatile memory devices, operating methods thereof and memory systems including the same
Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell...
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8427883 |
Setting circuit and integrated circuit including the same
A setting circuit includes a selection unit configured to select one of a predefined code and an external code in response to a test signal, and a setting information generation unit configured to...
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8427888 |
Word-line driver using level shifter at local control circuit
A representative circuit device includes a local control circuit having a level shifter, wherein in response to receipt of a first address signal the level shifter shifts the first address signal...
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8422318 |
Semiconductor device
A semiconductor device, including a plurality of control signal generation units each generating a control signal that is enabled when a column enable signal and a row enable signal are enabled,...
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8422327 |
Semiconductor device having nonvolatile memory element and manufacturing method thereof
To provide a semiconductor device including a pair of antifuse elements at either a high level or a low level, an OR circuit that outputs different logic information for a case that at least one of...
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8422330 |
Memory controller and memory controlling method
A memory controller includes: a first generating unit that generates a read-address to read a data element sequence having a plurality of data elements from a bank of a memory; a second generating...
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8422333 |
Semiconductor memory device and access method thereof
Example embodiments provide a semiconductor memory device that may include: a cell array arranged in pluralities of rows and columns; and a sense amplifier conducting writing and reading operations...
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8416609 |
Cross-point memory cells, non-volatile memory arrays, methods of reading a memory cell, methods of programming a memory cell, methods of writing to and reading from a memory cell, and computer systems
Cross-point memory cells, non-volatile memory arrays, methods of reading a memory cell, methods of programming a memory cell, and methods of writing to and reading from a memory cell are described....
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8416625 |
System and method for bit-line control using a driver and a pre-driver
In one embodiment, a bit-line driver has a first driver having a source terminal coupled to a high-voltage supply bus and a drain terminal coupled to the bit-line, and a second driver having a...
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8416638 |
Semiconductor memory device removing parasitic coupling capacitance between word lines
A semiconductor memory device includes a main word line shared by a plurality of mats. Each of the mats includes a plurality of sub word lines. A decoding unit is configured to decode a row address...
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8411509 |
Memory and method for charging a word line thereof
A memory and method for charging a word line thereof are disclosed. The memory includes a first word line driver, a first word line and a first switch. The first word line driver is connected to a...
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8411478 |
Three-dimensional stacked semiconductor integrated circuit
Various embodiments of a three-dimensional, stacked semiconductor integrated circuit are disclosed. In one exemplary embodiment, the circuit may include a master slice, a plurality of slave slices,...
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8411528 |
Semiconductor device capable of adjusting memory page size based on a row address and a bank address
A semiconductor device includes a memory cell array comprising a plurality of banks and a page size controller. The page size controller decodes a part of a bank selection address or a power supply...
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8411487 |
Semiconductor memory device
Regardless of a resistance state of a variable resistance element of a memory cell that is a target of a writing action (erasing and programming actions), an erasing voltage pulse for bringing the...
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8406056 |
Semiconductor memory device capable of increasing writing speed
A memory cell array has a structure in which a plurality of memory cells connected with word lines and bit lines and connected in series are arranged in a matrix form. A selection transistor...
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8400805 |
Semiconductor device
A semiconductor device according to the present invention includes plural controlled chips CC0 to CC7 that hold mutually different layer information, and a control chip IF that supplies in common...
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8400866 |
Voltage boosting in MRAM current drivers
A current driving mechanism for a magnetic memory device, comprising: a) a current driver circuit; and b) a current decoding block coupled to the current driver circuit, wherein the current...
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8400864 |
Mechanism for peak power management in a memory
A mechanism for managing peak power in a memory storage array that includes sub-array blocks may reduce the peak currents associated with read and write operations by staggering the wordline signal...
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8400804 |
Memory devices having break cells
A representative memory device includes a cell array, at least one break cell that subdivides the cell array into bit cell arrays, and one or more power switches that are electrically coupled to...
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8400865 |
Memory macro configuration and method
A memory macro comprises a plurality of memory array segments, each having a predetermined number of data inputs and outputs. A segment decoder circuit is configured to: receive a first value...
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8400869 |
Semiconductor memory module
A semiconductor device includes a plurality of semiconductor memories, a clock signal synchronization circuit, and a first circuit. The clock signal synchronization circuit is electrically coupled...
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8400851 |
Output enable signal generation circuit of semiconductor memory
An output enable signal generation circuit of a semiconductor memory includes: a latency signal generation unit configured to generate a latency signal for designating activation timing of a data...
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8400863 |
Configurable memory block
Circuits for a memory array and a method of operating a configurable memory block are disclosed. An embodiment of the disclosed memory circuits includes a first memory block coupled to a second...
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8400835 |
Non-volatile semiconductor memory
When a plurality of non-volatile memory cells in a memory cell array are simultaneously written, bit lines of the plurality of non-volatile memory cells are connected to M data lines, where M is an...
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8395962 |
Semiconductor memory device and method for operating the same
A semiconductor memory device includes a source signal generation unit configured to generate a source pulse signal having a pulse width which is determined depending on an interval between an...
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8395964 |
Row address decoder and semiconductor memory device having the same
A row address decoder includes a first main word line decoding unit decoding first and second row addresses to generate first to fourth main decoding signals. When a data storage test is performed,...
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