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7372755 On-chip storage memory for storing variable data bits  
An improved on-chip storage memory and method for storing variable data bits, the memory including an on-chip storage memory system for storing variable data bits that has a memory for storing data...
7370140 Enhanced DRAM with embedded registers  
An enhanced DRAM contains embedded row registers in the form of latches. The row registers are adjacent to the DRAM array, and when the DRAM comprises a group of subarrays, the row registers are...
7369453 Multi-port memory device and method of controlling the same  
A multi-port memory device providing various frequencies for ports is disclosed. The multi-port memory device includes a memory core, a clock generator and a plurality of ports. The clock generator...
7369447 Random cache read  
A non-volatile memory is described that utilizes a cache read mode of operation, where a next page of memory is being read/sensed from the memory array by the sense amplifiers while a previously...
7366049 Apparatus and method for updating data in a dual port memory  
A dual port memory is updated at substantially the same data sampling rate as a clock frequency of the dual port memory. The dual port memory stores data relating to each different parameter value...
7366007 Semiconductor memory device  
A semiconductor memory device capable of performing a high-speed write operation at lower voltage without increasing the word line activation period at normal voltage. The memory device has a write...
7359276 Multi-port system for communication between processing elements  
An aspect of the invention relates to communication between a first processing element and a second processing element. A first-in-first-out circuit (FIFO) includes a data input port, a data output...
7359275 Reduced size dual-port SRAM cell  
A dual-port Static Random Access Memory (SRAM) cell is disclosed that includes a storage element that is operable to store a data bit and a complement data bit. The dual-port SRAM cell further...
7349285 Dual port memory unit using a single port memory core  
A dual port memory implemented using a single port memory core. In an embodiment, the access requests from the two ports are processed in a single memory clock cycle. In one implementation, the...
7340558 Multisection memory bank system  
A serial communications architecture for communicating between hosts and data store devices. The Storage Link architecture is specially adapted to support communications between multiple hosts and...
7339825 Nonvolatile semiconductor memory with write global bit lines and read global bit lines  
A nonvolatile semiconductor memory is capable of dual and triple operation with a small chip size. A plurality of sectors is formed. Each sector has nonvolatile memory cells, local bit lines...
7333388 Multi-port memory cells  
A memory array comprises memory cells of the dynamic type having a first and a second port. A cache memory is connected to the address and data paths of the first and second ports. A refresh...
7330392 Dual port semiconductor memory device  
A dual port semiconductor memory device, including PMOS scan transistors, is provided. The dual port semiconductor memory device includes two PMOS transistors, two NMOS pull-down transistors, two...
7319632 Pseudo-dual port memory having a clock for each port  
A pseudo-dual port memory has a first port, a second port, and an array of six-transistor memory cells. A first memory access is initiated upon a rising edge of a first clock signal received onto...
7319619 Programmable logic device memory blocks with adjustable timing  
Programmable logic device integrated circuits with adjustable register and memory address decoder circuitry are provided. The integrated circuits contain programmable memory blocks and programmable...
7313049 Output circuit of a memory and method thereof  
An output circuit of a memory is provided. The output circuit includes a first pre-charge circuit, coupled to a read bit line which is coupled to a plurality of memory cells, pre-charging the...
7313031 Information processing apparatus and method, memory control device and method, recording medium, and program  
A memory control device for writing to a memory data input via a port section and for reading from the memory data output via the port section includes setting means for setting, in accordance with...
7313021 Nonvolatile memory circuit  
A nonvolatile memory circuit includes a flip-flop to degrade an internal circuit irreversibly based on a voltage applied to a first or second bit line so as to latch data in a nonvolatile manner, a...
7307892 Semiconductor integrated circuit  
A function switching part has a pair of programming elements programmed to different logic values. A decision circuit in the function switching part outputs a logic level according to a difference...
7307891 Fast memory circuits and methods  
A storage circuit using a dual-access memory includes means for alternately activating one access, then the other, with a maximum frequency equal to twice the maximum possible frequency of...
7307457 Apparatus for implementing dynamic data path with interlocked keeper and restore devices  
A keeper device for dynamic logic includes a first keeper path statically coupled to a dynamic data path, the first keeper path configured to prevent false discharge of the dynamic data path during...
7305516 Multi-port memory device with precharge control  
There is provided a multi-port memory device, which is capable of preventing a first high data fail phenomenon at an initial operation in a current sensing type global data bus...
7290079 Device and method for small discontiguous accesses to high-density memory devices  
A memory architecture design and strategy is provided using memory devices that would normally be considered disadvantageous, but by accommodating the data input, output, and other peripheral...
7289372 Dual-port memory array using shared write drivers and read sense amplifiers  
Dual port memory blocks that have a reduced layout area are provided. The write drivers and sense amplifiers are shared between the dual ports to reduce the number of write drivers and sense...
7286438 Dual port memory cell with reduced coupling capacitance and small cell size  
A dual or multi port memory device including a first group of bit lines associated with the first port a second group of bit lines associated with the second port, wherein the bit lines are...
7286437 Three dimensional twisted bitline architecture for multi-port memory  
A memory array of dual part cells has a pair of twisted write bitlines and a pair of twisted read bitlines for each column. The twist is made by alternating the vertical position of each bitline...
7286415 Semiconductor memory devices having a dual port mode and methods of operating the same  
A memory device having a dual port function includes a memory cell array and a switching unit. The memory cell array has a first port and a second port. The switching unit assigns first data...
7285832 Multiport single transistor bit cell  
A multiport memory cell ( 200, 300, 600 ) includes a first word line (WL 1 ) coupled to a gate electrode of a first transistor ( 201, 301, 601 ). A second word line (WL 2 ) is coupled to a gate...
7281094 Balanced bitcell for a multi-port register file  
In a multi-port register file of a storage unit within a processor, an improved bitcell design for storing a data bit is disclosed. The bitcell comprises a first set of read bitlines having a first...
7280427 Data access circuit of semiconductor memory device  
A data access circuit of a semiconductor memory device in which data is read and written via all multiple ports in the semiconductor memory device having a multi-port structure. The data access...
7277353 Register file  
In one embodiment, a memory circuit comprises one or more first memory cells, each of the one or more first memory cells configured to store at least one bit; one or more second memory cells, each...
7274589 Semiconductor storage device  
An SRAM cell 1 includes inverters 10, 20 , N-type FETs 32, 34, 36, 38 , word lines 42, 44 , bit lines 46, 48 , and voltage applying circuits 50, 60 . The voltage applying circuits 50, 60 ...
7269089 Divisible true dual port memory system supporting simple dual port memory subsystems  
A random access memory circuit and a method for configuring the same. The circuit includes a first array of memory cells including a first plurality of ports and a second plurality of ports, and a...
7269088 Identical chips with different operations in a system  
In some embodiments, a chip includes a memory core, control circuitry, and first ports, second ports, and third ports. The first ports are to only receive signals, the second ports are to only...
7269077 Memory architecture of display device and memory writing method for the same  
A memory architecture of display device comprises a memory cell array having a plurality of memory cells arranged as a plurality of cell rows and a plurality of cell columns, and a data latch...
7266028 Method and apparatus for bit mapping memories in programmable logic device integrated circuits during at-speed testing  
Programmable logic devices may use shadow memory for gathering diagnostic information while testing memory blocks. Memory block testing may be performed at any clock speed allowed during normal...
7262833 Circuit for addressing a memory  
A circuit is proposed which has a memory to which input data can be written at different write addresses with a first clock rate and from which output data can be read at different read addresses...
7260008 Asynchronous first-in-first-out cell  
The present invention discloses an asynchronous first-in-first-out cell, wherein modified Muller C elements are used to reduce the complexity of the circuit of the asynchronous first-in-first-out...
7257129 Memory architecture with multiple serial communications ports  
A serial communications architecture for communicating between hosts and data store devices. The Storage Link architecture is specially adapted to support communications between multiple hosts and...
7254680 Semiconductor integrated circuit and data processing system  
To enhance the speed of first access (read access different in word line from the previous access) to a multi-bank memory, multi-bank memory macro structures are used. Data are held in a sense...
7254088 Semiconductor memory  
In a multiport memory, in the event of simultaneous read/write operation for the same row address, a read word line pulse signal, output from a read control circuit for memory access based on an...
7251188 Memory access interface for a micro-controller system with address/data multiplexing bus  
A memory access interface for connecting a memory to a micro-controller having an address/data multiplexing bus and a microprocessor is proposed. The memory access interface includes an address...
7251186 Multi-port memory utilizing an array of single-port memory cells  
A multi-port memory device with an array of single-port memory cells is disclosed. According to one embodiment of the invention, the multi-port memory device has N number of memory ports, and is...
7251185 Methods and apparatus for using memory  
In an aspect, a method is provided for using memory. The method includes the steps of (1) employing memory stacking, memory mirroring and memory interleaving in a total memory to reduce a number of...
7251175 Very small swing high performance asynchronous CMOS static memory (multi-port register file) with power reducing column multiplexing scheme  
The present invention relates to a multi-port register file memory or SRAM including a plurality of storage elements and other circuitry that operate synchronously or asynchronously, and a method...
7248491 Circuit for and method of implementing a content addressable memory in a programmable logic device  
According to one aspect of the invention, a circuit for accessing data in a memory is disclosed. The circuit generally comprises a first port having a read logic circuit and a first output which...
7242633 Memory device and method of transferring data in memory device  
According to one aspect of the invention, a circuit for accessing data in a memory is disclosed. The circuit generally comprises a first port having a read logic circuit and a first output which...
7239572 Multiport memory  
This multiport memory has a memory hold circuit, a plurality of write circuits and read circuits, and a read/write capability regulating circuit. The read/write capability regulating circuit...
7233542 Method and apparatus for address generation  
A system for generating one or more common address signals for multi-port memory arrays. The system includes circuitry receiving one or more read address signal; circuitry receiving one or more...
7230873 Forced pulldown of array read bitlines for generating MUX select signals  
An apparatus, a method, and a computer program product are provided for time reduction in an array read access control consisting of a bitcell and a pulldown device outside of the bitcell. To...
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