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7391669 Semiconductor memory device and core layout thereof  
A semiconductor memory device of one aspect includes a memory cell block including n global word lines, and corresponding m sub word lines for each of the n global word lines, where n and m are...
7391668 Integrated circuit device and electronic device  
An integrated circuit device, a first direction being a direction extending from a first side which is a shorter side of the integrated circuit device to a third side opposed to the first side, a...
7391660 Address path circuit with row redundant scheme  
An address path circuit with a row redundant scheme may include an address buffer for buffering an external address to output an internal address, a command buffer for buffering a plurality of...
7391657 Semiconductor memory chip  
A semiconductor memory chip includes: a reception interface section for receiving external data, command, and address signals in form of serial signal frames; an intermediate data buffer for...
7388804 Semiconductor memory device for driving a word line  
A semiconductor memory device for driving a word line is provided. The enabling timing of a word line is advanced using a block information signal that contains no redundancy information, thereby...
7388801 Reduction of fusible links and associated circuitry on memory dies  
The number of fusible links and other circuit components required to provide memory cell redundancy are reduced by sharing physical memory locations among address banks that store memory addresses....
7388792 Memory management device and memory device  
A memory management device for managing a nonvolatile semiconductor memory which comprises a plurality of blocks, and permits data to be erased in units of one block, the memory management device...
7388774 SRAM including bottom gate transistor  
Bit lines in SRAM array are multi-divided, so that a segment read circuit is connected to local bit line, which circuit serves as amplifying transistor of an amplifier with load device of a block...
7385863 Semiconductor memory device  
A semiconductor memory device enabling efficient repair of defects by using limited redundant memory while suppressing a drop of access speed accompanied with the repair of defects of the memory,...
7385858 Semiconductor integrated circuit having low power consumption with self-refresh  
A dynamic random access memory has logically identical circuits for providing the same logical control signals. Each set of control signals can have different electrical parameters. One circuit can...
7383416 Method for setting a second rank address from a first rank address in a memory module  
A method for setting an address of a rank in a memory module having a number of memory chips distributed along a byte lane includes setting the first memory chip of the byte lane to have a first...
7382650 Method and apparatus for sector erase operation in a flash memory array  
A memory device is provided which includes a substrate, a common P-well isolated from the substrate, a plurality of sectors, and a common sector selection transistor configured to select one of the...
RE40356 Large-capacity semiconductor memory with improved layout for sub-amplifiers to increase operational speed  
A semiconductor memory such as a dynamic RAM having memory mats each divided into a plurality of units or sub-memory mats. Each sub-memory mat comprises: a memory array having sub-word lines and...
7379374 Virtual ground circuit for reducing SRAM standby power  
A method of operating a memory circuit having a plurality of blocks of memory cells ( 400 - 404 ) is disclosed. The method includes storing data in the plurality of blocks of memory cells. A first...
7379363 Method and apparatus for implementing high speed memory  
Various methods and apparatuses permit high speed reads of memory. Portions of data are copied and stored on other word lines. By reading a copy of data that is stored on memory cells accessed by a...
7379362 Semiconductor memory device having a hierarchical bit line structure  
In semiconductor memory devices having hierarchical bit line structures, a transfer transistor provided between a main bit line and a sub-bit line hinders achievement of a high speed and a low...
7379349 Simultaneous and selective memory macro testing  
A semiconductor device includes: a plurality of memory macros, each of which includes a plurality of memory cells, is activated in accordance with a corresponding active macro selection signal, and...
7379323 Memory with a refresh portion for rewriting data  
This memory comprises a first frequency detecting portion detecting access frequencies with respect to a plurality of memory cell blocks respectively, a comparator comparing the access frequencies...
7376791 Memory access systems and methods for configuring ways as cache or directly addressable memory  
A memory system is described. A processor provides a data access address, and selectively configures a selected number of the ways of a memory device as cache memory belonging to a cacheable...
7376034 Parallel data storage system  
A parallel data storage system for storing data received from, or retrieving data to, a host system using multiple data storage devices. The system includes an interface for communicating with the...
7375998 Ferroelectric random access memory circuits for guarding against operation with out-of-range voltages and methods of operating same  
A method of operating a ferroelectric random access memory (FRAM) can include reading a low-voltage FRAM monitoring memory array and preventing a read/write-back of an FRAM memory cell array if...
7372749 Methods for repairing and for operating a memory component  
In a method for repairing a memory component, data retention times of regular memory cells are determined. Weak regular memory cells having a data retention time that is shorter than a...
7370252 Interleaving apparatus and method for orthogonal frequency division multiplexing transmitter  
An interleaving apparatus and method for an OFDM transmitter are provided. The interleaving apparatus comprises a memory unit, a memory write/read control unit, a memory access address generation...
7370161 Bank arbiter system which grants access based on the count of access requests  
Provided are an arbiter capable of improving memory access efficiency in a multi-bank memory, a memory access arbitration system including the arbiter, and an arbitration method thereof, where the...
7369454 Semiconductor integrated circuit device  
A semiconductor integrated circuit device comprises several blocks including a word line connected with a memory cell, a row decoder selecting the word line, and a block decoder selecting the...
7369445 Methods of operating memory systems including memory devices set to different operating modes and related systems  
A method of operating a memory system including a plurality of memory devices coupled to a command address bus may be provided. In particular, a first memory device of the plurality of memory...
7369444 Early read after write operation memory device, system and method  
A memory device, system and method for allowing an early read operation after one or more write operations is provided according to an embodiment of the present invention. The memory device...
7366821 High-speed memory system  
A memory system has a memory controller and a plurality of memories. The plurality of memories are connected via a switch to an end of a bus, which is connected to the memory controller, wherein...
7362649 Memory control device and memory control method  
There is provided memory control device and memory control method, which can prevent wiring complication by many crossing wirings, and reduction of yield and quality. When a memory control device...
7362648 Memory system, memory device, and output data strobe signal generating method  
An output data strobe signal generating method and a memory system that includes a plurality of semiconductor memory devices, and a memory controller for controlling the semiconductor memory...
7362643 Semiconductor-memory device and bank refresh method  
A semiconductor memory device has a plurality of banks in which operations are performed for the banks in accordance with a command supplied from an external controller. The semiconductor memory...
7362638 Semiconductor memory device for sensing voltages of bit lines in high speed  
The present invention relates to a semiconductor memory device for sensing voltages of bit lines in high speed. The semiconductor memory device for sensing voltages of bit lines in high speed...
7359280 Layout structure for sub word line drivers and method thereof  
A layout structure for sub word line drivers and method thereof. The example layout structure may include at least one N-channel transistor arrangement having a cross sectional width and a cross...
7359279 Integrated circuit memory array configuration including decoding compatibility with partial implementation of multiple memory layers  
An integrated circuit having a three-dimensional memory array provides for a given number of memory planes, but may be fabricated instead to include a lesser number of memory planes by omitting the...
7359274 Semiconductor memory device  
A semiconductor memory device includes: a memory cell array having a plurality of data select lines disposed in parallel with each other, a plurality of data transfer line disposed in parallel with...
7359273 Semiconductor memory device having layout for minimizing area of sense amplifier region and word line driver region  
A semiconductor memory device has a layout that minimizes the area required for sense amplifier and word line driver regions. In the semiconductor memory device of the present invention, decoding...
7359269 Semiconductor memory device for reducing peak current during refresh operation  
A semiconductor memory device comprises a plurality of banks, each having first and second cell mats, each having a plurality of word lines; a data access controller for selecting a word line from...
7359260 Repair of memory cells  
A memory device has at least one sub array of memory cells having data columns and at least one spare sub array having spare columns. In one embodiment the sub array of memory cells and the sub...
7359253 Semiconductor memory device with input buffer  
A semiconductor memory device that includes an input buffer being inputted a write data from outside to buffer the write data and a control circuit putting the input buffer into an inactive state...
7359242 Semiconductor memory device with small number of repair signal transmission lines  
In an embodiment, a semiconductor memory device has a small number of repair signal transmission lines. The semiconductor memory device includes m repair redundancy blocks, each including n repair...
7355872 Segmented content addressable memory architecture for improved cycle time and reduced power consumption  
A content addressable memory (“CAM”) system includes a plurality of segments arranged in an array, wherein each of the plurality of segments includes a plurality of CAM cells, each of the...
7352648 Semiconductor memory  
At least one complete cell array having a predetermined memory capacity and an incomplete cell array having a capacity smaller than the predetermined memory capacity are arranged in one direction....
7352647 Reduced power usage in a memory for a programmable logic device  
A method and system to reduce power usage of memory within a programmable logic device (PLD) is disclosed. In one embodiment, a memory block is formed from a plurality of memory sub-blocks. A data...
7352646 Semiconductor memory device and method of arranging a decoupling capacitor thereof  
A semiconductor memory device with improved operational performance by reducing the level variation of first and second power voltages applied to a sense amplifier by efficiently locating a...
7352633 Multibit memory cell  
Provided are a method, system and device for storing multiple bits into a multibit memory cell. In the illustrated embodiment, each multibit memory cell is a “quadbit” cell capable of storing 4...
7352621 Method for enhanced block management  
A method and apparatus is described herein for managing bad blocks/sectors in a nonvolatile memory. Upon detecting an input/output fault to a target block in a nonvolatile memory, the target block...
7352612 Method for operating a data storage apparatus employing passive matrix addressing  
In a method for reducing detrimental phenomena related to disturb voltages in a data storage apparatus employing passive matrix addressing, particularly a memory device or a sensor device, an...
7350016 High speed DRAM cache architecture  
A high speed DRAM cache architecture. One disclosed embodiment includes a multiplexed bus interface to interface with a multiplexed bus. A cache control circuit drives a row address portion of an...
7349284 Memory array with staged output  
Embodiments of the present invention provide a method and system for staging the data output from an addressable memory location as a plurality of fields. In embodiments, each field of a data item...
7349279 Memory Device Having a Configurable Oscillator for Refresh Operation  
A dynamic random access memory device includes banks of dynamic memory cells. The device performs a refresh operation in response to receiving a self refresh command, by refreshing rows of the...
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