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7313046 Semiconductor memory devices in which the number of memory banks to be refreshed may be changed and methods of operating the same  
A semiconductor memory device includes a plurality of memory banks. A refresh control block is responsive to a control address that identifies at least one of the plurality of memory banks to be...
7313036 Memory device having open bit line architecture for improving repairability and method of repairing the same  
In a memory device having an open bit line architecture for improving repairability and a method of repairing the memory device, redundant memory cells used to repair defective cells are included...
7313023 Partition of non-volatile memory array to reduce bit line capacitance  
The present invention that partitions a memory array in N segments by switchably partitioning the bit lines in the array. In the exemplary embodiment, a top set of sense amps control the even bit...
7313009 Pattern layout of word line transfer transistors in NAND flash memory which executes subblock erase  
A semiconductor device includes a memory cell array, first word lines, second word lines and interconnection switching region. The memory cell array includes electrically rewritable nonvolatile...
7310266 Semiconductor device having memory cells implemented with bipolar-transistor-antifuses operating in a first and second mode  
A DAC having a memory mat including a plurality of first memory cells, and a plurality of output lines connected to the plurality of first memory cells. Each of the plurality of memory cells has a...
7310258 Memory chip architecture with high speed operation  
A semiconductor memory device includes at least one data transmission block including data I/O pads arranged in a major-axis side of the semiconductor memory device; a command and address...
7307913 Clock control device for toggling an internal clock of a synchronous DRAM for reduced power consumption  
A clock control device includes a set circuit for triggering an input address in response to an internal command signal to output a first address, a shift register including a plurality of...
7307912 Variable data width memory systems and methods  
Systems and methods disclosed herein provide for variable data width memory. For example, in accordance with an embodiment of the present invention, a technique for doubling a width of a memory is...
7307903 Method for testing memory device  
Disclosed is a method for testing a memory device, which can test a memory cell block while testing another memory cell block, so as to catch a process defect of the memory device within a short...
7307899 Reducing power consumption in integrated circuits  
A method and apparatus for reducing power consumption in integrated memory devices is provided. Banks of memory cells may be individually put into “sleep” mode via respective “sleep”...
7305517 Structure of sequencers that perform initial and periodic calibrations in a memory system  
A structure of sequencers, a method, and a computer program are provided for performing initial and periodic calibrations in an XDR™ memory system. A memory controller that performs these...
7305516 Multi-port memory device with precharge control  
There is provided a multi-port memory device, which is capable of preventing a first high data fail phenomenon at an initial operation in a current sensing type global data bus...
7304910 Semiconductor memory device with sub-amplifiers having a variable current source  
A column circuit that amplifies signals read from a sense amplifier array SAA to local input/output lines LIO in sub-amplifiers SAMP to transfer the amplified signals to main input/output lines MIO...
7304908 SRAM device capable of performing burst operation  
Memory devices are provided which are capable of performing burst operations by simultaneously writing/reading a plurality of data bits to/from memory in response to a selection of a single...
7304900 Semiconductor memory  
In a semiconductor memory having a plurality of memory banks that can be independently accessed, remedying bit registers that are substituted for defective memory cells are respectively provided...
7304877 Semiconductor memory device with uniform data access time  
A semiconductor memory device includes: a core region having a plurality of bank sets for outputting/storing a data in response to an inputted address, wherein each bank set includes one bank, one...
7301850 Content addressable memory (CAM) devices having bidirectional interface circuits therein that support passing word line and match signals on global word lines  
Content addressable memory devices include a bidirectional interface circuit configured to receive word line signals from a plurality of global word lines and pass match information from a selected...
7301847 Method and device for a main board commonly associated with DDR2 or DDR1  
A method and device for a main board commonly shared with DDR2 or DDR1 includes allowing the main board being associated with a voltage transducer and a DDR2 connector, the voltage transducer...
7301844 Semiconductor device  
In a semiconductor device, an internally-generated power supply voltage VPP is monitored. If the internally-generated power supply voltage VPP is lower than a lower limit voltage, serial refresh is...
7301793 Semiconductor memory device  
A semiconductor memory device comprises a plurality of memory cell groups. Each memory cell group includes at least two memory cells. Each memory cell group includes a read section and a write...
7301791 Semiconductor device  
A semiconductor device capable of accessing to the memory with a high speed, and comprising a memory with a large capacity. The semiconductor device comprises a plurality of memory banks (Bank) 1 ...
7298662 Semiconductor device with power down arrangement for reduce power consumption  
A synchronous DRAM is provided which includes arrangements for operations of power supply circuitry based upon whether the DRAM is in a power down mode or not. In one embodiment, a first power...
7298655 Isolation control circuit and method for a memory device  
A semiconductor memory includes a memory cell array, a sense amplifier, an isolation device interposed between the sense amplifier and a bit line of the memory cell array, and circuitry for...
7295486 Memory and driving method therefor  
A memory and a driving method therefor is provided. A j-th bank select MOS transistor is coupled to a j-th bit line and controlled by a bank select line. A j-th BD region is coupled to the j-th...
7295485 Memory architecture with advanced main-bitline partitioning circuitry for enhanced erase/program/verify operations  
The present invention provides a solution for long master bit lines in a large capacity memory device. A master bit line is partitioned by at least one switching transistor placed on the master bit...
7295482 Semiconductor memory device for a low voltage operation  
A semiconductor memory includes first and second cell arrays for applying a data signal onto pairs of first bit lines and second bit lines, respectively, first and second reference cell blocks each...
7292487 Independent polling for multi-page programming  
A method of testing, polling and trimming memory pages in different memory banks simultaneously is presented, using a cache memory located in each one of the memory banks. The cache memory is at...
7292472 Memory device capable of stable data writing  
A memory device according to the present invention includes a memory cell array including a plurality of memory cells arranged therein, the memory cell array being divided into a plurality of...
7290098 Method and apparatus for interleaving data streams  
In one embodiment, an optimized interleaving instruction is provided. The interleaving instruction facilitates a bit-level interleaving of two streams of data stored in two source registers into a...
7290079 Device and method for small discontiguous accesses to high-density memory devices  
A memory architecture design and strategy is provided using memory devices that would normally be considered disadvantageous, but by accommodating the data input, output, and other peripheral...
7289385 Bank selection signal control circuit for use in semiconductor memory device, and bank selection control method  
Memory bank selection control circuits and methods are provided which improve the data sensing margin for data sense amplifiers in a multi-bank semiconductor memory structure. In one aspect, a bank...
7289384 Method for writing to multiple banks of a memory device  
In a multi-bank memory system such as a synchronous dynamic random access memory (SDRAM), a method of writing data to the banks is provided. This method allows for writing to any number of banks....
7289383 Reducing the number of power and ground pins required to drive address signals to memory modules  
One embodiment of the present invention provides a system that reduces the number of power and ground pins required to drive address signals to system memory. During operation, the system receives...
7289369 DRAM hierarchical data path  
A hierarchical DRAM array, DRAM macro and logic chip including the DRAM macro embedded in the logic. DRAM array columns are segmented with a small number (e.g., 2-64) of cells connected to a local...
7287118 Maintaining an average erase count in a non-volatile storage system  
Methods and apparatus for maintaining an average erase count in a system memory of a non-volatile memory system are disclosed. According to one aspect of the present invention, a method for...
7287115 Multi-chip package type memory system  
A multichip package type memory system is disclosed, which comprises a plurality of types of memory integrated circuits which are provided in a memory system in a package having an internal bus,...
7286433 Method for activating a plurality of word lines in a refresh cycle, and electronic memory device  
An electronic memory device for storing data comprises a memory cell array arranged in at least one memory bank and comprising memory cells in which information is stored. The electronic memory...
7286401 Nonvolatile semiconductor memory device  
Disclosed here is a nonvolatile semiconductor memory device used to prevent data loss that might occur in unselected memory cells due to a disturbance that might occur during programming/erasing...
7286398 Semiconductor device and method of controlling said semiconductor device  
A semiconductor device includes: groups of memory cells that are connected to word lines; and select gates that are controlled by control word lines and are connected to the groups of memory cells,...
7286395 Current driven switched magnetic storage cells having improved read and write margins and magnetic memories using such cells  
A method and system for providing a magnetic memory is described. The magnetic memory includes a plurality of magnetic storage cell and at least one bit line and a plurality of source lines...
7286385 Differential and hierarchical sensing for memory circuits  
A memory circuit includes multiple word lines, multiple pairs of complementary bank bit lines, multiple block select lines, and multiple of block circuits. Each of the block circuits includes a...
7286380 Reconfigurable memory block redundancy to repair defective input/output lines  
An embodiment of the present invention is a technique to provide a reconfigurable repair circuit in a memory device. A table structure contains a plurality of entries, each entry having a defective...
7283420 Multi-port memory device  
The present invention proposes a multi-port memory device for preventing a degradation of a global data drive efficiency by turning off the switches which do not discharge a global data bus. The...
7283419 Integrated semiconductor memory  
An integrated semiconductor memory device includes a first memory zone, a second memory zone, first address connections and a second address connection. A second address signal present at the...
7283418 Memory device and method having multiple address, data and command buses  
A dynamic random access memory (“DRAM”) device includes a pair of internal address buses that are selectively coupled to an external address bus by an address multiplexer, and a pair of...
7283417 Write control circuitry and method for a memory array configured with multiple memory subarrays  
Write control circuitry and control method are provided for a memory array configured with multiple memory subarrays. The write control circuitry includes multiple subarray write controllers...
7280426 Semiconductor device with non-volatile memory and random access memory  
A semiconductor device including a large capacity non-volatile memory and at least one random access memory, said the access time of said device being matched to the access time of each random...
7280401 High speed data access memory arrays  
Techniques for reading data from memory cells in memory arrays are provided. Local read bit lines are coupled to logic gates such as NAND gates. The input terminals of each logic gate are coupled...
7280398 System and memory for sequential multi-plane page memory operations  
A system and method for performing memory operations in a multi-plane flash memory. Commands and addresses are sequentially provided to the memory for memory operations in memory planes. The memory...
7280386 Method and system for controlling refresh to avoid memory cell data losses  
A DRAM includes a register storing subsets of row addresses corresponding to rows containing at least one memory cell that is unable to store a data bit during a normal refresh cycle. Each subset...
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