Matches 1 - 50 out of 897 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >
Match Document Document Title
7631138 Adaptive mode switching of flash memory address mapping based on host usage characteristics  
In a non-volatile memory storage system such as a flash EEPROM system, a controller switches the manner in which data sectors are mapped into blocks and metablocks of the memory in response to host...
7627712 Method and system for managing multi-plane memory devices  
A computational system comprising a controller and a multi-plane solid state memory device accessible to the controller is disclosed. The controller is configured to provide access to a virtual...
7616520 Integrated circuit device and electronic instrument  
An integrated circuit device having a display memory which stores data for at least one frame from among image information displayed in a display panel which has a plurality of scan lines and a...
7613866 Method for controlling access to a multibank memory  
The present invention relates to a method for scheduling and controlling access to a multibank memory having at least two banks, and to an apparatus for reading from and/or writing to recording...
7613070 Interleaved input signal path for multiplexed input  
System and method for latching input signals from multiplexed signal lines. An input signal path includes a command path and an address path. In one embodiment, a command latch of the command path...
7610430 System and method for memory hub-based expansion bus  
A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also...
7609569 System and method for implementing row redundancy with reduced access time and reduced device area  
A system for implementing row redundancy in integrated circuit memory devices includes one or more main subarrays having word line, bit line and memory cell devices, each of the one or more main...
7606110 Memory module, memory unit, and hub with non-periodic clock and methods of using the same  
A memory module, a memory unit, and a hub with a non-periodic clock and methods for using the same. An example memory module may include a phased locked loop, receiving an external, periodic clock...
7596035 Memory device bit line sensing system and method that compensates for bit line resistance variations  
Systems, devices and methods are disclosed, such as a system and method of sensing the voltage on bit lines that, when respective memory cells coupled to the bit lines are being read that...
7593270 Integrated circuit device and electronic instrument  
An integrated circuit device has a display memory which stores data for at least one frame displayed in a display panel which has a plurality of scan lines and a plurality of data lines. The...
7590015 Integrated circuit device and electronic instrument  
An integrated circuit device includes a data driver block, a memory block, an information storage block in which an address of a defective cell of the memory block is programmed and stored as a...
7584335 Methods and arrangements for hybrid data storage  
Embodiments may comprise a hybrid memory controller to facilitate accesses of more than on type of memory device, referred to generally hereafter as a hybrid memory device or hybrid cache device....
7580295 Semiconductor memory device and memory system including semiconductor memory device  
A semiconductor memory device comprises a memory cell array comprising memory cells of a first type. The memory cell array performs write and read operations in response to signals designed for the...
7580294 Semiconductor memory device comprising two rows of pads  
A semiconductor memory device includes a first row of pads including a first plurality of data input/output (I/O) pads; a second row of pads including a second plurality of data I/O pads; and a...
7577059 Decoding control with address transition detection in page erase function  
Circuits and methods are provided for controlling multi-page erase operations in flash memory. The page address of each address of a multi-page erase operation is latched in wordline decoders. A...
7577783 Portable data storage device and method of dynamic memory management therefor  
A portable data storage device includes a first storage unit having a data storing zone and a reserved zone for bad blocks in the first storage unit, and a second storage unit having a look-up...
7577011 Optimization of ROM structure by splitting  
A method for designing a read-only memory (ROM), and related device, includes partitioning a dataset into two or more sub-datasets that each have the same address space, but are of a smaller...
7573760 Integrated circuit for sampling a sequence of data packets at a data output  
An integrated circuit comprises a sampling circuit arranged at a data output of an operating section and operated by sampling edges, data packets appearing at the data output in response to a...
7573778 Semiconductor memory device  
A semiconductor memory device has a command decoder responsive to a plurality of commands to set the semiconductor memory device to a normal mode, for generating control signals corresponding to...
7570505 Memory based computation systems and methods for high performance and/or fast operations  
A high performance logic circuit optimizes a digital logic function by dividing the function into smaller blocks. Thus, the logic circuit is divided into smaller blocks. The smaller blocks are...
7570542 Circuit and method for generating data output control signal for semiconductor integrated circuit  
The data output control signal generating circuit includes a delay correction signal generating unit that delays an input signal by a phase difference between a clock and a delay locked loop clock,...
7567481 Semiconductor memory device adapted to communicate decoding signals in a word line direction  
A semiconductor memory device comprising decoding signals communicated solely in a word line direction is provided. The semiconductor memory device comprises a sub-array comprising a plurality of...
7558123 Efficient and systematic measurement flow on drain voltage for different trimming in flash silicon characterization  
Systems and methods that facilitate characterization of a flash memory device are presented. A characterization component can be associated with a regulator component included in a memory device to...
7558909 Method and apparatus for wide word deletion in content addressable memories  
A system and method for searching and deleting segmented wide word entries in a CAM array is disclosed. A normal CAM search operation is executed to find the first word segment of a wide word. Once...
7558144 Circuit for controlling pulse width of auto-refresh signal and circuit for generating internal row address for auto refresh  
A circuit for controlling a pulse width of a refresh signal is provided. The circuit includes a first pulse width controller for receiving a first refresh signal having a first enable period, and...
7558131 NAND system with a data write frequency greater than a command-and-address-load frequency  
The invention provides methods and apparatus. A NAND flash memory device receives command and address signals at a first frequency and a data signal at a second frequency that is greater than the...
7555629 Memory card providing hardware acceleration for read operations  
A memory card comprises a memory controller connected to a non-volatile memory module. The memory controller comprises a first circuit adapted to convert a first external address into a first...
7554830 Semiconductor device with non-volatile memory and random access memory  
A semiconductor device including a large capacity non-volatile memory and at least one random access memory, said the access time of said device being matched to the access time of each random...
7548479 Semiconductor memory device and manufacturing method thereof  
A semiconductor memory device includes: a memory array; an internal address supplying unit configured to produce a first internal address in response to an external address; a first fuse unit...
7539811 Scaleable memory systems using third dimension memory  
A non-volatile scalable memory circuit is described, including a bus formed on a substrate that includes active circuitry, metallization layers, and a plurality of high density third dimension...
7539077 Flash memory device having a data buffer and programming method of the same  
A flash memory device includes a memory cell array with multiple memory cells, a data buffer, a write driver and a controller. The data buffer stores data to be programmed into the memory cells,...
7535749 Dynamic memory word line driver scheme  
A circuit which accurately controls the word line (pass transistor gate) driving voltage to a voltage which is both controlled and is not significantly greater than is needed to drive the word...
7525853 Semiconductor device and method for boosting word line  
A semiconductor device of the present invention includes a booster circuit that boosts a selected word line (WL) to a given voltage higher than a power supply voltage and a charge pump circuit that...
7515831 System and method for auto-configuring a telecommunication device with an embedded controller  
The present invention is a telecommunication device with an auto-configurable capability that supports both serial and parallel data interfaces. The telecommunication device can transfer...
7515500 Memory device performance enhancement through pre-erase mechanism  
The specification and drawings present a new method, apparatus and software product for performance enhancement of a memory device (e.g., a memory card) using a pre-erase mechanism. The memory...
7515159 Reconfigurable address generation circuit for image processing, and reconfigurable LSI comprising the same  
A reconfigurable address generation circuit for image processing is configured to an arbitrary state based on configuration data generates a read address for reading out image data of pixel units...
7505299 Semiconductor memory device  
A semiconductor memory device that can achieve high-speed operation or that is highly integrated and simultaneously can achieve high-speed operation is provided. Transistors are disposed on both...
7505351 Data output circuit of semiconductor memory apparatus and method of controlling the same  
The data output circuit for a semiconductor memory apparatus includes a plurality of pads in which a range of use is determined such that the respective pads are used exclusively in each of at...
7499352 Integrated circuit having memory array including row redundancy, and method of programming, controlling and/or operating same  
An integrated circuit device (for example, a logic device (such as, a microcontroller or microprocessor) or a portion of a memory device (such as, a discrete memory)), including (a) a memory cell...
7492569 Capacitor cell, semiconductor device and process for manufacturing the same  
A capacitor cell for reducing noise in a high drive cell includes a plurality of vias for supplying power to an interconnection layer positioned over the capacitor cell from an upper...
7489589 MRAM internal clock pulse generation with an ATD circuit and the method thereof  
A magnetic random access memory having an extended address transition detection circuit having a chip enable input, a chip write enable input, a data bus connection, and an address bus connection....
7483334 Interleaved input signal path for multiplexed input  
System and method for latching input signals from multiplexed signal lines. An input signal path includes a command path and an address path. In one embodiment, a command latch of the command path...
7483331 Semiconductor memory, memory system, and operation method of memory system  
A memory system includes a semiconductor memory having a plurality of banks; and a controller accessing the semiconductor memory. The number of the banks is larger than the number of banks...
7471589 Semiconductor memory devices, block select decoding circuits and method thereof  
Semiconductor memory devices, block select decoding circuits and a method of activating a word line are provided. An example semiconductor memory device may include a plurality of memory banks....
7468931 Memory device and method for operating a memory device  
A memory arrangement having a memory area with a plurality of memory locations, to which external addresses can be allocated, and an address decoder which is coupled to the memory area and which...
7463535 Memory modules and memory systems having the same  
A memory module includes a port configured to receive write data and command/address signals and multiple memory devices. The multiple memory devices include a first set of the memory devices, each...
7460430 Memory devices having reduced coupling noise between wordlines  
Memory devices configured to reduce coupling noise between adjacent wordlines in a memory array. More specifically, wordline drivers are interleaved such that adjacent wordlines are driven by...
7450461 Semiconductor memory device and transmission/reception system provided with the same  
In a system of using a plurality of memories with a plurality of CPUs, a plurality of memory arrays are placed on the same memory chip with each memory array being individually provided with a...
7437527 Memory device with delayed issuance of internal write command  
A method and apparatus for storing data in a memory device is described. The apparatus is configured to perform the following steps. The method employs a two-step technique which allows the...
7417881 Low power content addressable memory  
A low power content addressable memory (CAM) device. The CAM device receives an N-bit comparand value and, in response, activates less than N compare lines within the CAM device to compare each of...
Matches 1 - 50 out of 897 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >