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6968469 |
System and method for preserving internal processor context when the processor is powered down and restoring the internal processor context when processor is restored
A CPU ( 1 ) automatically preserves the CPU context in a computer memory ( 5 ) that remains powered-up when the CPU is powered down in sleep mode. By means of the preserved CPU context, the CPU is...
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6958946 |
Memory storage device which regulates sense voltages
A memory storage device includes a memory cell configurable to have at least a first conductive state and includes a first and second conductor each electrically coupled to the memory cell. A...
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6958947 |
Semiconductor memory device with internal voltage generators for testing a memory array and peripheral circuits
A semiconductor memory device which includes an internal voltage generator circuit for adjusting an external power supply voltage and generating first and second internal power supply voltages. The...
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6931481 |
Battery firmware customer/field update method
A method and system for upgrading a programmable battery unit in a mobile information handling system. The method and system make use of unique address words, checks, and comparisons stored in...
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6922368 |
Apparatus and structure for rapid enablement
A method and apparatus of reducing the time for enabling a dynamic random access memory (DRAM) upon initial application of power, comprises generating an internal RAS signal upon initial power up...
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6917556 |
Static memory cell having independent data holding voltage
A static memory cell, composed of cross-coupled MOS transistors having a relatively high threshold voltage, is equipped with MOS transistors for controlling the power supply line voltage of the...
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6918002 |
Data processor and data processing method reduced in power consumption during memory access
When the CPU writes data into a memory, a 0 detection circuit detects the number of bits having the value 0 from the data. When the number of bits with 0 is equal to or larger than the number of...
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6889298 |
Battery-based secured storage binding system
An apparatus and method for exclusively binding data to a data processing system. The logical binding apparatus of the present invention includes a detachable circuit device mounted within a system...
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6876593 |
Method and apparatus for partial refreshing of DRAMS
Memory devices, refresh logic and approaches to selectively refresh each row of memory cells within a memory device depending on whether or not each is marked as having data to be preserved.
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6871269 |
Data processing system and a method of distributing accesses to memories
The present invention relates to a data processing system comprising a processor ( 100 ), at least one data memory ( 132 ), at least one program memory ( 134 ) and a main bus ( 110 ), common to the...
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6871291 |
Method for recording power failure time of a computer system
A method for recording power failure time of a computer system. The computer system includes a power supply for generating a power signal, a memory for recording data, and a processor for...
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6862236 |
Ferroelectric memory device with an equalization circuit connected between word voltage supply lines and bit voltage supply lines
A ferroelectric memory device has a function of protecting data held in memory cells from an unexpected unstable power supply voltage generated when the power is turned on or off, or when reading...
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6851015 |
Method of overwriting data in nonvolatile memory and a control apparatus used for the method
In a nonvolatile memory such as flash memory where data is stored sector by sector, a method of overwriting a data sector is provided. The old data to be overwritten in a data sector along with its...
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6845055 |
Semiconductor memory capable of transitioning from a power-down state in a synchronous mode to a standby state in an asynchronous mode without setting by a control register
A semiconductor memory that can make the transition from a power-down state in a synchronous mode to an asynchronous mode without setting by a control register and that needs no extra circuits. A...
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6839299 |
Method and structure for reducing gate leakage and threshold voltage fluctuation in memory cells
A memory device has a memory cell including a plurality of active devices, which can be switched on by an applied threshold voltage. A power line is coupled to at least one storage node by one of...
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6836824 |
Method and apparatus for reducing power consumption in a cache memory system
A method for operating a cache having a sleep mode is provided. The cache is located within a memory hierarchy of a computer system, and the method is comprised of receiving a first cache request,...
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6829185 |
Method for precharging memory cells of a dynamic semiconductor memory during power-up and semiconductor memory
In a semiconductor memory, during the rewriting of the signal stored in a memory cell, a displacement current is produced in the cell capacitor, which has to be supplied by an on-chip plate...
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6819622 |
Write and erase protection in a synchronous memory
A synchronous flash memory includes an array of non-volatile memory cells, and has a package configuration that is compatible with an SDRAM. The memory device includes a memory array, a...
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6812555 |
Memory card substrate with alternating contacts
A memory card substrate includes a first solder pad assembly formed on a top edge of the memory card substrate. The first solder pad assembly has multiple first solder pads equally spaced from each...
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6804752 |
Event data protection method for a flash programmable microprocessor-based control module
A flash programmable microprocessor-based control module is operated in a manner to protect the integrity of event data stored in the programmable memory of the module while permitting authorized...
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6795362 |
Power controlling method for semiconductor storage device and semiconductor storage device employing same
A method for controlling power for a semiconductor storage device and the semiconductor storage device are provided which enable power consumption to be greatly reduced in a standby state. The...
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6791886 |
SRAM cell with bootstrapped power line
A memory cell includes at least one active device for selectively connecting a supply voltage node to a power line. The power line couples capacitive elements through the at least one active device...
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6781909 |
Semiconductor memory device and method for controlling semiconductor memory device
A semiconductor memory device, which performs refreshing for data retention, provided with a power down mode that stops refreshing. The device includes a request generation circuit, which generates...
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6768355 |
Transient rejecting circuit
A transient rejecting system for protecting the state of a memory is described. The transient rejecting system includes a signal transfer circuit and a charge storage circuit coupled to at least...
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6765826 |
Write protection control for electronic assemblies
The invention relates to an electronic assembly having a non-volatile memory device with a controllable write protection feature and a switching configuration for generating a write protection...
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6765828 |
Non-volatile semiconductor storage device and method of reading out data
A non-volatile semiconductor storage device provided with a boost circuit for setting, for at least a certain period of time, a source line selectively connected to a memory cell to a negative...
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6762958 |
Semiconductor memory with precharge control
The application of a nonactive level to a word line in a semiconductor memory is controlled by a precharge control. In order to initiate the precharge operation, a pair of reference bit lines are...
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6751147 |
Method for adaptively writing a magnetic random access memory
A method of adaptively writing magnetic memory cells of a MRAM is disclosed according to an embodiment of the present invention. The method comprises providing a logical data block of a memory...
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6744686 |
Semiconductor memory module with low current consumption
A semiconductor memory module with a changeover device by which an internal voltage supply circuit can be switched on or off in a simple manner. The changeover device has two evaluation circuits,...
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6744689 |
Semiconductor memory device having a stable internal power supply voltage
A semiconductor memory device is provided with a power supply circuit. The power supply circuit includes a reference voltage generating circuit which generates a first reference voltage, a booster...
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6735141 |
Semiconductor memory device having an SRAM and a DRAM on a single chip
A semiconductor memory device includes an SRAM provided on a chip, the SRAM including an SRAM cell array. A DRAM is provided on the chip, the DRAM including a DRAM cell array. An address input...
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6735142 |
Power-up control circuit with a power-saving mode of operation
A power-up control circuit has three components including a normal power-supply voltage level detection section, a special command section for detecting a deep-sleep enable input signal, and an...
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6735117 |
Hold-up power supply for flash memory
A hold-up power supply for flash memory systems is provided. The hold-up power supply provides the flash memory with the power needed to temporarily operate when a power loss exists. This allows...
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6731527 |
Architecture for a semiconductor memory device for minimizing interference and cross-coupling between control signal lines and power lines
A semiconductor memory device is organized in such a way that undesirable interference and cross-coupling between various signals generated during operation of the device is minimized. The...
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6731563 |
Data backup device and step-up/step-down power supply
When a power supply detection unit 5 detects an OFF command of a battery 2 , a DRAM 1 is changed to a self-refresh mode. Then, power is fed from a backup power supply 4 to the DRAM 1.
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6724678 |
Nonvolatile semiconductor memory unit
A nonvolatile semiconductor memory unit which is provided with a nonvolatile semiconductor memory and a controller for performing a read operation, a write operation and an erase operation on the...
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6721212 |
Memory control circuit and control system for a plurality of memories interconnected via plural logic interfaces
A memory control circuit includes a controller ( 1 A) for controlling a RAM ( 13 ) conforming to the standard where source voltage is 2.5 V (SSTL2 standard), and a nonvolatile memory ( 14 )...
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6707748 |
Back up power embodied non-volatile memory device
A back up power embodied non-volatile memory device including a connection port, a power supply unit and a memory system. A host machine provides data and power to the connection port through an...
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6696862 |
Semiconductor memory device input circuit
A semiconductor memory device input circuit including a clock selection portion. The clock selection portion receives an internal clock signal before a data strobe signal is enabled. The input...
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6693840 |
Non-volatile semiconductor memory device with enhanced erase/write cycle endurance
The power-supply unit, while directing externally supplied power to the control unit and the like, accumulates an amount of power that is required by the control unit to save data from the volatile...
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6690605 |
Logic signal level converter circuit and memory data output buffer using the same
A circuit configuration for converting logic signal levels has two level converters, to which an input signal to be converted is fed complementarily. The level converters generate a rising or...
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6675255 |
Device initialize command for a synchronous memory
A synchronous flash memory includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. In one embodiment, the present invention...
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6674681 |
Semiconductor integrated circuit
A semiconductor integrated circuit ( 100 ) that may determine whether or not a power supply voltage has dropped to a level that data integrity in a RAM portion ( 15 ) may be lost has been...
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6643209 |
Apparatus for using volatile memory for long-term storage
A structure including volatile memory devices that are used by the host computer system as the storage media. The volatile memory devices include volatile memory device back up systems to provide...
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6639826 |
Memory cell operation using ramped wordlines
The standby power consumption of storage or memory cells is improved by ramping the wordline voltage down at a rate slow enough to allow the addressed storage cell to reach a more stable voltage...
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6625741 |
Arrangement for a security module
In an arrangement for a security module that is plugged via an interface onto a base plate of a postal device, particularly a postage meter machine, the battery is replaceably arranged on the...
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6618312 |
Method and device for providing a multiple phase power on reset
A method and apparatus is provided for performing an intelligent power-on-reset, and enabling the verification of a current voltage level with a reconfigurable brown out reset voltage level. In...
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6614708 |
Non-volatile memory device with built-in laser indicator
A non-volatile memory device with a built-in laser indicator. The non-volatile memory device includes a connective port, a buffer, a non-volatile memory unit, a memory controller, a battery and a...
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6611473 |
Power-saving modes for memories
A system and a method are disclosed for providing a power saving mode during reading a memory device. A new memory content is read from the memory and, before being put at the memory output bus, is...
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6584032 |
Dynamic random access memory having a low power consumption mode, and method of operating the same
An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the...
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