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7120070 Method for testing the serviceability of bit lines in a DRAM memory device  
DRAM memory device ( 1 ) comprising at least one array of memory cells ( 2, 3, 4, 5 ), each memory cell ( 12 ) being connected to a bit line (BL) and a word line (WL), each of said bit lines (BL)...
7116154 Low power charge pump  
A low power charge pump is disclosed. A pump driving node of a first pump stage is selectively coupled to a pump driving node of the subsequent pump stage. Subsequent to a transfer of charge from a...
7112895 Reduced power consumption in integrated circuits with fuse controlled redundant circuits  
System and method for reducing power consumption in integrated circuits (IC) with fuse controlled redundant circuits. A preferred embodiment comprises detecting the status of fuses within the IC,...
7110314 Semiconductor memory device and method for initializing the same  
A semiconductor memory device includes memory cell blocks ( 11 ) through ( 14 ) including a nonvolatile memory cell. The memory cell blocks ( 11 ) through ( 14 ) include chip-data storing regions (...
7102939 Semiconductor memory device having column address path therein for reducing power consumption  
There is provided a semiconductor memory device capable of reducing power consumption by preventing unnecessary operations of an AL flip-flop delay unit and a CL flip-flop delay unit. The...
7102953 Semiconductor memory device capable of operating at high speed and with low power consumption while ensuring reliability of memory cell  
A monitor circuit for monitoring external potential EXTVDD and variable delay circuit determine the time interval in which signal ZODACT is being at the L level according to the potential level of...
7102954 Semiconductor integrated circuit device having logic circuit and dynamic random access memory on the same chip  
In a memory circuit, a transistor formed in the same process as that of a logic transistor is used for peripheral circuitry except for a region to be supplied with high voltage. Thus, the...
7098689 Disabling unused/inactive resources in programmable logic devices for static power reduction  
A method of operating a programmable logic device, including the steps of enabling resources of the programmable logic device being used in a circuit design implemented by the programmable logic...
7092309 Standby mode SRAM design for power reduction  
A method and system is disclosed for controlling power supply to a memory device. After determining at least one word line being selected, supply voltage lines are controlled so that a...
7088636 Semiconductor memory circuit  
The present invention provides a semiconductor memory circuit capable of reducing current consumption at non-operation in a system equipped with a plurality of chips that share the use of a power...
7085946 Backup memory control unit with reduced current consumption having normal self-refresh and unsettled modes of operation  
A backup memory control unit can reduce the current consumption when a memory (SDRAM) is inactive by providing the memory with an unsettled mode in which no power is supplied to the memory. It...
7081897 Unified memory organization for power savings  
Positioning a block of graphics memory within a memory system so as to minimize the number of memory devices and/or banks of memory within memory devices occupied by the block of graphics memory so...
7082076 Memory module with hierarchical functionality  
A hierarchical memory structure having memory cells, and sense amplifiers and decoders coupled with the memory cells to form first tier memory module, and subsequent tiers being formed by having...
7082062 Voltage output control apparatus and method  
When the output of a boosted voltage is started by a boosted voltage generation circuit, the voltage supplied to memory cells and level shift circuits side through a current mirror circuit is...
7079441 Methods and apparatus for implementing a power down in a memory device  
A power down is implemented in a memory device capable of performing a read operation in which data and a data strobe signal are supplied as outputs. The power down techniques includes generating a...
7079447 Dynamical adaptation of memory sense electronics  
A circuit and a method are given, to realize a dynamically adapting response speed behavior of memory sense electronics for Sense Electronics Endowed (SEE) memory devices. Fast memories use sense...
7072235 Bias sensing in DRAM sense amplifiers through coupling and decoupling device  
Voltage coupling/decoupling devices are provided within DRAM devices for improving the bias sensing of sense amplifiers and thus the refresh performance. The voltage coupling/decoupling devices...
7068386 Image processing system, image data processing method, and storage medium  
This invention provides an image processing system which is built by connecting a host device which reads out and executes program data stored in a storage medium, and a device added with a card...
7064589 Semiconductor device using two types of power supplies supplying different potentials  
A semiconductor device which is driven by a first potential, a second potential lower than the first potential, and a third potential lower than the second potential includes a first Pch transistor...
7064984 Circuit and method for reducing leakage current in a row driver circuit in a flash memory during a standby mode of operation  
A row driver receives an input signal and a test mode signal, and is coupled to first and second voltage sources and has an output coupled to a word line. The row driver operates in an active mode...
7061820 Voltage keeping scheme for low-leakage memory devices  
The present invention facilitates memory device operation by mitigating power consumption during suspend modes of operation, also referred to as sleep/data retention modes. This is accomplished by...
7057916 Small size ROM  
The invention concerns a ROM circuit ( 40 ) including columns of storage cells, each column being connected to a bit site (BLi, BLi+1), wherein the columns are arranged in groups of two adjacent...
7057960 Method and architecture for reducing the power consumption for memory devices in refresh operations  
A method for reducing power consumption during background operations in a memory array with a plurality of sections comprising the steps of (i) controlling the background operations in one or more...
7057959 Semiconductor memory having mode register access in burst mode  
A method for controlling a semiconductor memory in which a mode register can be set in a burst mode. To set an operation mode in the burst mode, the semiconductor memory is changed first from the...
7051219 System and apparatus for adjusting a clock speed based on a comparison between a time required for a scheduler function to be completed and a time required for an execution condition to be satisfied  
A method of scheduling a CPU in which a clock of the CPU is controlled depending upon the states of processes to reduce power consumption. The clock is controlled by substituting clock functions of...
7042789 Energy storing memory circuit  
The invention relates to a memory arrangement having an energy storage device (store) which collects the energy transported during the flowing of a write or read current and makes it available for...
7042781 Semiconductor memory device for reducing write recovery time  
A semiconductor memory device for reducing a data recovery time includes a cell block having a plurality of unit cells, each for storing a data; a command control block for receiving an activation...
7035155 Dynamic memory management  
In a method, system and apparatus for management of dynamic memory in battery-powered devices, information is stored in dynamic memory, such as SDRAM chips. Chip partitioning minimizes the number...
7036032 System for reduced power consumption by phase locked loop and method thereof  
A system and method are provided for reducing power consumption within a video processing portion of a system. Activity associated within a video-processing portion of a personal digital assistant...
7023261 Current switching for maintaining a constant internal voltage  
A semiconductor memory device includes a voltage reduction circuit which reduces a power supply voltage and outputs an internal voltage, a nonvolatile memory connected to the internal voltage and a...
7023754 Semiconductor device having standby mode and active mode  
An internal potential generation circuit of an SDRAM includes a standby VDDS generation circuit which has a relatively low current driving force and which generates an internal power supply...
7023755 Low power control circuit and method for a memory device  
A memory device with a low power control circuit that reduces power while ensuring that the device remains in a low power mode until a high power mode has been requested. The low power control...
7023761 Programmable stackable memory array system  
Systems and methods are provided for reducing power consumption in the form of leakage current in a memory array. One embodiment discloses a memory array system. The memory array system comprises a...
7020040 Utilizing an ACPI to maintain data stored in a DRAM  
A method and related apparatus for utilizing an ACPI to maintain data stored in a DRAM includes a processor, a DRAM, a south bridge chipset, and a rechargeable battery device. The south bridge...
7012840 Semiconductor memory device having voltage driving circuit  
The present invention relates to a semiconductor memory device having a voltage driving circuit. The semiconductor memory device includes: a core voltage node; a first driving unit having a first...
7009902 Semiconductor memory having a first and second sense amplifier for sensing a memory cell voltage during a normal mode and a refresh mode  
Semiconductor memory apparatus and methods of operating the same are provided. The apparatus has at least one first sense amplifier for amplifying a voltage level which has been read from a memory...
7006400 Content addressable memory with reduced instantaneous current and power consumption during a search  
The power required to search a content addressable memory (CAM) is substantially reduced by forming the CAM to have a number of CAM banks with a corresponding number of power switches that control...
7002870 Speeding up the power-up procedure for low power RAM  
An internal power system for a low power memory chip is described that provides a large capacity internal power source during chip power up and during an active state whereby memory operations are...
7000065 Method and apparatus for reducing power consumption in a memory bus interface by selectively disabling and enabling sense amplifiers  
A method and apparatus for selectively disabling sense amplifiers to reduce power consumption in a memory bus interface are disclosed. The method includes amplifying data signals from a memory bus...
6996023 Semiconductor memory device capable of reducing current consumption in active mode  
There is provided a semiconductor memory device which is capable of reducing a current consumption in an active mode. The semiconductor memory device includes an internal voltage supply block and...
6992946 Semiconductor device with reduced current consumption in standby state  
In order to reduce a gate-source leakage current in a standby state, the gate insulating film of one of transistors in each of inverters IV 1 –IV 5 is made thick. In a standby state, an input...
6990034 Static semiconductor memory device and method of controlling the same  
A plurality of p-MOSFETs connected to a power supply line is turned on to precharge bit lines. A precharge cancel signal generated by a NOR circuit and an inverter performs precharge control to...
6990035 Circuit and method for reducing SRAM standby power  
A method of operating a memory circuit to reduce standby current is disclosed. The method includes applying a first voltage (Vdd) to a power terminal ( 224 ) of a memory cell having a first ( 612 )...
6990031 Semiconductor memory device control method and semiconductor memory device  
In a semiconductor memory device which requires a refresh operation, a control method stops supplying a word line voltage which is a boosted voltage higher than an external supply voltage, a memory...
6980047 Low power high voltage ramp-up control circuit  
A circuit, and a method, provide low power high voltage ramp-up control for on-chip semiconductor power supplies, efficiently generating on-chip high voltage to support programming of electrically...
6977519 Digital logic with reduced leakage  
A power gate structure and corresponding method are provided for controlling the ground connection of a logic circuit for a plurality of modes, where the power gate structure includes an NFET...
6977860 SRAM power reduction  
A SRAM uses a number of memory banks in a configuration that uses lower voltage swings on a differential internal data bus so that the internal data bus no longer uses single-ended VDD/VSS,...
6975551 Semiconductor storage, mobile electronic device, and detachable storage  
While a memory section ( 1 ) is in standby mode, a power supply/interruption circuit ( 2 ) supplies electric power to a memory section ( 1 ) only during periods in which a refresh operation is...
6967890 Battery power measuring system and method for a battery-backed SRAM  
A battery power measuring system for a Battery-Backed SRAM includes a nonvolatile memory ( 11 ), a clock ( 12 ), a CPU ( 10 ) and a buzzer ( 13 ). The nonvolatile memory is for storing a system...
6967891 Information processing apparatus and semiconductor memory  
An information processing apparatus or a semiconductor memory according to the present invention periodically refreshes a high-speed nonvolatile memory cell having spontaneous data storing...
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