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7292496 Semiconductor memory circuit  
The present invention provides a semiconductor memory circuit capable of reducing current consumption at non-operation in a system equipped with a plurality of chips that share the use of a power...
7292485 SRAM having variable power supply and method therefor  
A memory circuit has a memory array with a first line of memory cells, a second line of memory cells, a first power supply terminal, a first capacitance structure, a first power supply line coupled...
7292494 Internal power management scheme for a memory chip in deep power down mode  
A method for a deep power down mode is described for a memory chip in which voltage regulators and charge pumps are turned off, memory cell voltages are floated, and support circuit internal power...
7286435 Memory card device having low consumed power in the consumed power state  
A card device has a regulator ( 5 ), a first internal circuit ( 6 ) and a second internal circuit ( 7 ), and the regulator supplies, to the second internal circuit, an internal voltage generated by...
7286389 Low-power, p-channel enhancement-type metal-oxide semiconductor field-effect transistor (PMOSFET) SRAM cells  
Low-power, all-p-channel enhancement-type metal-oxide semiconductor field-effect transistor (PMOSFET) SRAM cells are disclosed. A PMOSFET SRAM cell is disclosed. The SRAM cell can include a latch...
7277333 Power savings in active standby mode  
Apparatus for reducing the power consumed by a memory device selectively activates a power saving mode in which operation of a delay compensation circuit may be suspended during an active power...
7277344 Semiconductor storage device and operating method therefor  
A semiconductor storage device according to an embodiment of the present invention includes: a plurality of word lines; a plurality of memory cells corresponding to the plurality of word lines; and...
7269082 Chip enable control circuit, memory control circuit, and data processing system  
A CE control circuit includes a CE signal generating circuit which sets a CE signal to an enable level when bringing the memory to an operable state or sets the CE signal to a disable level when...
7266034 Data recording device  
An data recording device according to an aspect of the present invention includes a memory cell array in a memory chip, a refresh circuit which executes a refreshing of the memory cell array, a...
7266026 Symbol frequency leveling in a storage system  
Methods and apparatus for transforming data into a format which may be efficiently stored in a non-volatile memory are disclosed. According to one aspect of the present invention, a method for...
7256644 Semiconductor circuit device having hierarchical power supply structure  
Resistance elements are inserted into a main power supply line and a main ground line so that offset differential amplifiers receive voltages developed across the same. The differential amplifiers...
7251170 Peripheral voltage generator  
A peripheral voltage generator is provided for reducing an operating current by generating a peripheral voltage within a mobile SDRAM, and a current is used in a deep-power down mode and a self...
7251183 Static random access memory having a memory cell operating voltage larger than an operating voltage of a peripheral circuit  
A static memory cell, composed of cross-coupled MOS transistors having a relatively high threshold voltage, is equipped with MOS transistors for controlling the power supply line voltage of the...
7248533 Semiconductor circuit apparatus with power save mode  
A semiconductor circuit apparatus comprises a substrate and a circuit block including a memory formed on the substrate. The circuit block performs regular operations at a first power supply voltage...
7248506 Circuit arrangement having security and power saving modes  
Circuit arrangement having complementary data input nodes for reception of a dual rail data signal and complementary data output nodes for outputting a dual rail data signal. A connection switch is...
7248532 Device, system and method for reducing power in a memory device during standby modes  
A memory device responsive to standby mode commands for reducing internal operational power on a memory device is disclosed. The memory device includes a circuit for reducing power during a standby...
7239548 Method and apparatus for applying bias to a storage device  
In Step 1 , a bias is applied (ON) to all of vertical rows Z 1 ( 0 ) to Z 1 ( 2 ). With respect to the horizontal rows, a bias is not applied (OFF) to a horizontal row Z 2 ( 0 ) where the...
7227804 Current source architecture for memory device standby current reduction  
A memory device ( 200 ) can include a memory cell block ( 202 ), a standby current source ( 206 ), an active current source ( 208 ), and a clamping device ( 212 ). In a standby mode, a standby...
7218565 Method and apparatus for independently refreshing memory capacitors  
A method for refreshing a memory capacitor is provided. First, the refresh controller provides a refresh control signal. The pre-decoded row address counter counts and outputs a regular pre-decoded...
7218566 Power management of memory via wake/sleep cycles  
A method of managing power states of memory modules while performing memory access operations is discussed. Memory modules are in a power saving state until an access operation involving the module...
7209404 Low power memory sub-system architecture  
Disclosed methods and apparatus provide embedded memory architectures that lower the overall operational power consumption of memory arrays without sacrificing memory access speed. Because in large...
7206249 SRAM cell power reduction circuit  
A method is described that comprises modulating the power consumption of an SRAM as a function of its usage at least by reaching, with help of a transistor, a voltage on a node within an...
7203855 Power-saving control circuitry of electronic device and operating method thereof  
A power-saving control circuitry of an electronic device is provided. The power-saving control circuitry comprises a power control circuit, an oscillator, a clock pulse generator, a reserve circuit...
7200051 Semiconductor integrated circuit device having power supply startup sequence  
A semiconductor integrated circuit device, which drives a first region and a second region provided via capacitance to a positive internal power supply and a negative internal power supply...
7193883 Input return path based on Vddq/Vssq  
Input circuit configurations that reduce the amount of input signal jitter caused by a common input signal return path, methods and circuits utilizing the same are provided. Input signal return...
7184354 Memory device reduced power consumption in power down mode  
A memory device capable of reducing power consumption when the operation mode is a deep power down mode, includes an external power source voltage line through which an external power source...
7180815 Semiconductor integrated circuit device  
A semiconductor integrated circuit device with a power-on detecting circuit, wherein the power-on detecting circuit includes: first and second power supply terminals between which an external power...
7177981 Method and system for cache power reduction  
A method and system is disclosed for minimizing data array accesses during a read operation in a cache memory. The cache memory has one or more tag arrays and one or more data arrays. After...
7177222 Reducing power consumption in a data storage system  
An apparatus and associated method for reducing power consumption in an electronic circuit comprising a refresh load device being employed alternatively between an operational mode and a state...
7173845 User RAM flash clear  
A memory cell includes first and second p-channel transistors and first and second n-channel transistors in a cross-coupled latch configuration. Power control circuitry associated with the memory...
7173873 Device and method for breaking leakage current path  
A device and a method for breaking the leakage current path, wherein the leakage current is caused by a defect in a memory cell of a memory array, are provided. The device includes a column...
7170812 Semiconductor memory device capable of reducing power consumption during reading and standby  
The input data at address 0 is “00000000”, including many “0”s. The data at address 0 is inverted to “11111111”. At the same time, flag information “1” indicative of inversion...
7167990 Interfacing circuit for reducing current consumption  
An interfacing circuit for reducing current consumption includes a command decoder, an operation controller, and a transmission controller. The command decoder decodes input packet commands and...
7167407 Dynamic semiconductor memory device and power saving mode of operation method of the same  
A dynamic semiconductor memory device includes a memory cell array including a plurality of memory cells connected between a plurality of word lines and a plurality of bit line pairs. A mode...
7161866 Memory device tester and method for testing reduced power states  
A memory device tester capable of testing for proper operation of reduced power states in memory devices. The memory device tester can include a processor or a state machine, each configured to...
7158434 Self-refresh circuit with optimized power consumption  
A random access memory device has a memory array, and a refresh rate generator circuit. The memory array has a plurality of memory cells that are configured to hold a charge. The memory array has...
7154803 Redundancy scheme for a memory integrated circuit  
A redundancy scheme for a memory integrated circuit having at least two memory sectors and, associated with each memory sector, a respective memory location selector for selecting memory locations...
7154802 Semiconductor memory device capable of operating at high speed and with low power consumption while ensuring reliability of memory cell  
A monitor circuit for monitoring external potential EXTVDD and variable delay circuit determine the time interval in which signal ZODACT is being at the L level according to the potential level of...
7151703 Semiconductor memory device including global IO line with low-amplitude driving voltage signal applied thereto  
A semiconductor memory device including a global IO line with a low-amplitude driving voltage signal applied thereto. In the device, a first driver converts a data signal of a first voltage level...
7152167 Apparatus and method for data bus power control  
An approach for data bus power control. Data input sense amplifiers of a request agent are enabled prior to a data phase of a transaction according to a data bus power control signal. Once enabled,...
7149131 Semiconductor memory device and internal voltage generating method thereof  
A semiconductor memory device reduces power consumption with maintaining quality of an internal power voltage and a core voltage. The semiconductor memory device reduces power consumption with...
7145830 Semiconductor memory device  
A semiconductor memory device is provided which effectively reduces a consumption of current of a system of circuits associated with refresh operations. A control signal circuit 2 controls...
7139189 State-retentive mixed register file array  
A storage cell having a storage circuit and a readout circuit may be used in power-saving environments, where the storage circuit may be maintained in an ultra-drowsy mode during power-saving...
7138825 Charge recycling power gate  
A charge recycling power gate and corresponding method are provided for using a charge sharing effect between a capacitive load of a functional unit and a parasitic capacitance of a charge...
7139208 Refresh-free dynamic semiconductor memory device  
In a data holding mode, data storage in a one bit/one cell scheme in a normal operating mode are rearranged into data storage in a twin-cell mode in which data are stored in a one bit/two cell...
7135886 Field programmable gate arrays using both volatile and nonvolatile memory cell properties and their control  
The embodiments of the present invention relate to the general area of Field Programmable Gate Arrays and, in particular, to Field Programmable Gate Arrays (“FPGAs”) comprising memory cells...
7130233 Sensing circuit for single bit-line semiconductor memory device  
A sensing circuit for sensing logic data is shown. A memory cell is electrically connected to a bit line. The sensing circuit includes a first pre-charging module electrically connected to the bit...
7126834 Sense amplifier architecture for content addressable memory device  
A content addressable memory (CAM) device ( 200 ) can equalize a potential between a match line ( 202 ) and corresponding pseudo-supply (PVSS) line ( 204 ) in a pre-sense operation. In a sense...
7123533 Circuit and method for refreshing memory cells of a dynamic memory  
A circuit for refreshing memory cells of a dynamic memory contains a refresh control circuit for driving a memory cell array for accessing memory cells of the dynamic memory for a refresh process....
7123541 Memory with address management  
The present invention allows for the reduction in power consumption of memory devices. A memory device in one embodiment prohibits address signal propagation on internal address buses based upon a...
Matches 151 - 200 out of 945 < 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >