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7423899 SRAM device having forward body bias control  
A SRAM device is provided having a plurality of memory cells. Each memory cell may include a plurality of transistors coupled in a cross-coupled inverter configuration. An NMOS transistor may be...
7420873 Simplified power-down mode control circuit utilizing active mode operation control signals  
A power-down control circuit utilizes the control signals employed in an active mode operation to operate when a power-down mode entry command is received during an active mode operation. The...
7418612 Semiconductor device with a power down mode  
The semiconductor device with the power down mode includes a power down detecting block for generating a power down mode signal by detecting if the power down mode is activated, a power source...
7411847 Burn in system and method for improved memory reliability  
The present invention relates to a system and method for applying a stress to a hierarchical memory structure in parallel, testing the memory structure for weak defects. The present invention...
7412614 Power management using a pre-determined thermal characteristic of a memory module  
A computer system includes a memory module. Power management in the computer system is performed with at least one temperature rise parameter (ΔTx) of the memory module.
7408829 Methods and arrangements for enhancing power management systems in integrated circuits  
Methods and arrangements to configure power management systems for integrated circuits are provided herein. A group of IC components that are functionally distinct or have mutually exclusive and/or...
7408830 Dynamic power supplies for semiconductor devices  
This invention discloses a power supply management circuit which comprises at least one switching circuit coupled between a power supply and a power recipient circuit, and at least one voltage...
7404092 Power supply control in a server system  
An information handling system comprising at least one power supply unit (PSU), at least one blade server module (BSM) and at least one module monitor board (MMB). The at least one PSU, at least...
7400547 Semiconductor integrated circuit with power-reducing standby state  
A semiconductor integrated circuit has a sense amplifier which senses and outputs data read out from memory cells connected to word lines and bit lines, and a read-out control circuit which has a...
7400545 Storage circuit with efficient sleep mode and method  
A circuit and method efficiently powers a static storage element during a low voltage mode of operation. The static storage element is powered at a first voltage level in an active mode of the...
7400546 Low overhead switched header power savings apparatus  
A tri-state power gating apparatus for reducing leakage current in a memory array includes a first distributed header device coupled to the memory array, the first distributed header device is...
7397693 Semiconductor memory device with memory cells operated by boosted voltage  
A memory using an SRAM memory cell intended for low-voltage operation is designed to decrease the threshold value of MOS transistors constituting the memory cell without substantial decrease in the...
7397721 Standby leakage current reduction circuit and semiconductor memory device comprising the standby leakage current reduction circuit  
Embodiments of the invention provide a standby leakage current reduction circuit and a semiconductor memory device comprising the standby leakage current reduction circuit. The invention provides a...
7397708 Technique to suppress leakage current  
Embodiments of the invention generally provide a method and wordline driver having a reduced leakage current. In one embodiment, a wordline is driven to a boosted high voltage with a driver...
7394714 Circuit implementation of a dynamic power supply for SRAM core array  
A SRAM device includes at least one memory cell having a source line for receiving an internal supply power, and a voltage management circuit coupled to the source line for generating the internal...
7395466 Method and apparatus to adjust voltage for storage location reliability  
According to embodiments of the present invention, an integrated circuit such as a processor includes a counter to count an actual number of unreliable storage locations in the processor cache, at...
7394701 Circuit and method of driving a word line by changing the capacitance of a clamp capacitor to compensate for a fluctuation of a power supply voltage level  
A word line driving circuit includes a read voltage generator and a word line driver. The read voltage generator precharges a clamp capacitor with a power supply voltage to stably generate a read...
7391667 Semiconductor integrated circuit  
An apparatus is to reduce, during the standby time, the electric power caused by the leakage current flowing through a storage transistor in a 3-transistor dynamic cell. Source electrodes of...
7388800 Memory control device having less power consumption for backup  
When it is detected that the voltage of a main power supply is reduced below a predetermined value during a normal operation, a power controller switches a power supply for a DRAM from the main...
7385870 Semiconductor memory device and semiconductor integrated circuit device  
A leakage current of the MOS transistor of a power control section at a standby time is drastically reduced and the reduction of the consumption power is achieved. A memory module is provided with...
7382666 Power supply circuit for delay locked loop and its method  
A delay locked loop (DLL) power supply circuit for use in a semiconductor memory device, including: a DLL power supplier for supplying a DLL power supply voltage to a DLL in response to a reference...
7382676 Method of forming a programmable voltage regulator and structure therefor  
In one embodiment, a programmable voltage regulator stores data representing a programmable configuration of the regulator. The regulator is configured to verify the validity of the stored data...
7380048 System and method for managing data in memory for reducing power consumption  
A system or method to partition data in a memory based at least in part to a data type, and to refresh the memory based at least in part to the data type.
7379373 Voltage supply circuit, in particular for a DRAM memory circuit, as well as a method for controlling a supply source  
A voltage supply circuit for providing an internal supply voltage in an integrated circuit is provided. The voltage supply circuit comprises a supply source for setting the internal supply voltage...
7376038 Fast access memory architecture  
A computer system including a control logic and a storage coupled to the control logic. The storage includes a plurality of bitcells and bitlines used to transfer data between the control logic and...
7372763 Memory with spatially encoded data storage  
In some embodiments, the invention provides a chip with at least one memory circuit that comprises a majority voter circuit with first and second digitally controlled variable delay elements. The...
7372754 Method and apparatus for controlling slope of word line voltage in nonvolatile memory device  
A nonvolatile memory device includes a nonvolatile memory cell array including a plurality of nonvolatile memory cells connected to a plurality of word lines, a word line voltage generator...
7372746 Low voltage sensing scheme having reduced active power down standby current  
A low voltage sensing scheme reduces active power down standby leakage current in a memory device. During memory's active power down state, the leak current may increase because of the use of P and...
7366820 Second-cache driving/controlling circuit, second cache, RAM, and second-cache driving/controlling method  
A circuit for driving and controlling a second cache that is incorporated in a processor and comprises a plurality of RAM. The circuit comprises a second-cache control unit 1 A and a chip-enable...
7362646 Semiconductor memory device  
A semiconductor memory device includes a memory cell array provided in a cell array area and including a plurality of memory cells, a source potential line which applies a source potential to the...
7362641 Method and system for low power refresh of dynamic random access memories  
A method and system for operating a DRAM device in either a high power, full density mode or a low power, half density mode. In the full density mode, each data bit is stored in a single memory...
7360107 Method of controlling power within a disk array apparatus  
A power supply unit generates a predetermined voltage from power supplied from an external power supply and outputs the voltage to a power supply line. A battery charge/discharge circuit charges a...
7359277 High speed power-gating technique for integrated circuit devices incorporating a sleep mode of operation  
A high speed power-gating technique for an integrated circuit device having a Sleep Mode of operation comprises providing an output stage coupled between a supply voltage source and a reference...
7356717 Information processing apparatus with central processing unit and main memory having power saving mode, and power saving controlling method  
A power saving type information processing apparatus is provided which is not expensive and can provide a high interruption performance without using an expensive and dedicated memory and a...
7352645 Memory device  
A semiconductor memory device is provided. The semiconductor memory device includes a memory matrix having a plurality of memory cells arranged according to a plurality of rows and a plurality of...
7352611 Semiconductor integrated circuit  
Data breakdown due to fluctuation of an operation power source is suppressed by suppressing a sub-threshold leakage current. A semiconductor integrated circuit includes a pair of power source...
7345947 Memory array leakage reduction circuit and method  
Embodiments of the invention provide techniques for reducing standby power consumption due to leakage currents in memory circuits. In some embodiments, systems are provided with one or more...
7345931 Maintaining internal voltages of an integrated circuit in response to a clocked standby mode  
A method and circuit for controlling an output reference voltage generated by a reference voltage generator disposed on a memory device are provided. A signal for enabling a clocked standby mode of...
7339849 Internal voltage supply circuit of a semiconductor memory device with a refresh mode  
An internal voltage supply circuit may Include a first internal voltage generator for receiving an external voltage and generating a first internal voltage, a second internal voltage generator for...
7339822 Current-limited latch  
A current-limited latch circuit is used within a nonvolatile memory integrated circuit for decoding, programming, erase, and other operations. In one implementation, there are a number of latches...
RE40132 Large scale integrated circuit with sense amplifier circuits for low voltage operation  
Disclosed is a one-chip ULSI which can carry out the fixed operation in a wide range of power supply voltage (1 V to 5.5 V). This one-chip ULSI is composed of a voltage converter circuit(s) which...
7333380 SRAM memory device with flash clear and corresponding flash clear method  
A static memory device includes at least one memory cell with two cross-coupled CMOS inverters to be connected to first and second voltages. The substrate of the NMOS transistor of a first CMOS...
7327185 Selectable application of offset to dynamically controlled voltage supply  
An electronic system comprises a plurality of circuit paths. Each path in the plurality of circuit paths is coupled to receive a system voltage from a voltage supply. The system further comprises a...
7328413 Method and circuit for reducing leakage and increasing read stability in a memory device  
A device and method for increasing the read stability of a memory device includes sizing a sleep transistor according to a size ratio of the transistor relative to a driver transistor forming part...
7328356 Apparatus and method for saving power in a disk drive with a serial ATA interface connected to a host via a serial ATA bus  
In an electronic device with a serial ATA interface, upon detection of the issue or reception of a preset command, a confirmation device, such as a CPU, confirms the completion of execution of the...
7327598 High performance, low leakage SRAM device and a method of placing a portion of memory cells of an SRAM device in an active mode  
An SRAM device and a method of placing a portion of memory cells of an SRAM device in an active mode is provided. In one embodiment, the SRAM device includes a hierarchical grouping of memory cells...
7307913 Clock control device for toggling an internal clock of a synchronous DRAM for reduced power consumption  
A clock control device includes a set circuit for triggering an input address in response to an internal command signal to output a first address, a shift register including a plurality of...
7307907 SRAM device and a method of operating the same to reduce leakage current during a sleep mode  
An SRAM device and a method of operating an SRAM device. In one embodiment, the SRAM device includes (1) an SRAM array coupled to row peripheral circuitry by a word line and coupled to column...
7304910 Semiconductor memory device with sub-amplifiers having a variable current source  
A column circuit that amplifies signals read from a sense amplifier array SAA to local input/output lines LIO in sub-amplifiers SAMP to transfer the amplified signals to main input/output lines MIO...
7301846 Method and apparatus for increasing computer memory performance  
A method and apparatus for providing power to a memory array of a computer's memory subsystem, and more particularly power at a level greater than that available through the computer motherboard so...
Matches 101 - 150 out of 947 < 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >