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7623402 Semiconductor memory device operating a self refreshing and an auto refreshing  
An oscillating period of an oscillator is configured to be adjustable by CODEi output from a ROM circuit, and a circuit is configured so that the oscillating period is equal to a period p times a...
7623401 Semiconductor device including multi-bit memory cells and a temperature budget sensor  
One embodiment provides a semiconductor device including a plurality of multi-bit memory cells, a first temperature budget sensor, and a circuit. Each of the plurality of multi-bit memory cells is...
7619944 Method and apparatus for variable memory cell refresh  
Devices allow a system using a memory array, or the memory itself, to more efficiently control refresh intervals. This reduces standby current and the overhead associated with refresh operations....
7619943 Circuit and method for controlling self-refresh cycle  
The present invention relates to a circuit and a method for controlling a self-refresh cycle of a dynamic random access memory or DRAM. A cell voltage is directly detected so that a self-refresh...
7619942 Multi-port memory device having self-refresh mode  
The multi-port memory device includes a mode input/output controller for receiving a flag signal and generating a self-refresh entry signal and a self-refresh escape signal, a refresh interval...
7618186 Self-calibrating temperature sensors and methods thereof  
A self-calibrating temperature sensor and a method thereof are provided. The self-calibrating temperature sensor may include a reference voltage generator to generate a reference voltage based on...
7617356 Refresh port for a dynamic memory  
A refresh port for a dynamic memory. In one embodiment, an apparatus includes a memory and a refresh command interface to receive a refresh command including a portion indicating signal. Refresh...
7616508 Flash-based FPGA with secure reprogramming  
A flash-based programmable integrated circuit includes programmable circuitry, a flash memory array coupled to the programmable circuitry for configuring it, flash programming circuitry for...
7613883 Memory device with mode-selectable prefetch and clock-to-core timing  
In a memory device, either a first portion or a second, smaller portion of data retrieved from a storage array is loaded into a data buffer in accordance with a prefetch mode selection and then...
7613873 Deferring refreshes during calibrations in memory systems  
A memory system employs calibrations to ensure the precise transmission of data. During calibrations, memory refreshes can occur; however, these refreshes can interfere with calibration streams....
7613064 Power management modes for memory devices  
Embodiments of power management modes for memory devices are disclosed.
7613061 Method and apparatus for idle cycle refresh request in DRAM  
Generally, methods and apparatus are provided for idle cycle refresh request in a dynamic random access memory. According to one aspect of the invention, a dynamic random access memory is refreshed...
7613060 Methods, circuits, and systems to select memory regions  
Embodiments for selecting regions of memory are described. For example, in one embodiment a memory device having an array of memory cells includes an array selection block. The array selection...
7613032 Semiconductor memory device and control method thereof  
A semiconductor memory device includes a plurality of memory cells each including a first inverter and a second inverter, a first storage node connected to an output terminal of the first inverter...
7609576 Semiconductor memory device with refresh trigger  
A semiconductor memory device includes a memory cell array including a plurality of memory cell transistors, an X decoder designating a position of an X axis of the memory cell, a Y decoder...
7609566 Semiconductor memory device  
A semiconductor memory device includes a charge pumping circuit, a level sensor, an oscillator, and a pumping control signal generator. The charge pumping circuit performs a negative-pumping...
7606101 Circuit and method for controlling a clock synchronizing circuit for low power refresh operation  
A method and apparatus is provided for idling a clock synchronizing circuit during at least a portion of time during execution of a refresh operation in a memory device. In a memory device...
7602662 Row address control circuit in semiconductor integrated circuit and method of controlling row address using the same  
Disclosed are a row addresses control circuit of a semiconductor integrated circuit and method of controlling row addresses using the same. The circuit includes: a pulse generator receiving a bank...
7602661 Semiconductor memory apparatus and method of controlling the same  
A semiconductor memory apparatus configured to have general cells and redundant cells for repairing defective cells among the general cells includes; repair sets configured to determine whether...
7599244 Semiconductor memory, memory controller and control method for semiconductor memory  
A semiconductor memory for inputting and outputting data synchronously with a clock includes a clock reception unit for receiving the clock, and a command reception unit for initially receiving a...
7599208 Nonvolatile ferroelectric memory device and refresh method thereof  
A nonvolatile ferroelectric memory device is provided which includes a cell array including a plurality of nonvolatile memory cells each configured to read/write data, a refresh control unit...
7596038 Floating body control in SOI DRAM  
A system including a DRAM memory device on an integrated circuit (IC) using a control logic device to initiate a body refresh operation to provide a means for maintaining a low voltage at a...
7594750 Method for outputting internal temperature data in semiconductor memory device and circuit of outputting internal temperature date thereby  
A method for outputting internal temperature data in a semiconductor memory device can output, at high speed, relatively accurate temperature data externally, without continuously or periodically...
7593280 Semiconductor memory device operating with a lower voltage for peripheral area in power saving mode  
A semiconductor memory device reduces power consumption during a refresh operation. The semiconductor memory device comprises a voltage generator, a sensing controller, an output driver and a data...
7590021 System and method to reduce dynamic RAM power consumption via the use of valid data indicators  
A DRAM or SDRAM component maintains an indicator that indicates whether or not an independently refreshable memory unit of a DRAM array, such as a row, contains valid data. When a refresh operation...
7586807 Semiconductor memory device  
A semiconductor memory device includes a row control circuit block and a column control circuit block each performing an access control over a memory cell array, a data I/O circuit block...
7586805 Method and system for providing directed bank refresh for volatile memories  
A memory system is provided. The memory system includes a volatile memory having a number of banks and a memory controller configured to control the volatile memory to engage in an auto-refresh...
7584070 Testing/adjusting method and test control apparatus for rotating disk storage devices  
Embodiments of the invention provide a method of testing/adjusting magnetic disk devices, in which the method allows the tests/adjustments to be conducted by solving problems due to the data sizes...
7583553 Semiconductor memory and refresh cycle control method  
A semiconductor memory and a refresh cycle control method that reduce a standby current by properly changing a refresh cycle according to the temperature of the semiconductor memory. A temperature...
7583552 Method and system for providing independent bank refresh for volatile memories  
A memory system is provided. The memory system includes a volatile memory having a number of banks, each bank having a number of rows, and a memory controller configured to direct the volatile...
7583551 Power management control and controlling memory refresh operations  
A memory devices provide signals indicating when refresh operations are complete. The signals from a number of memory devices can be combined, such as by Oring, to provide a refresh complete signal...
7580310 Self refresh control device  
Disclosed herein is a self refresh control device for reducing a current leakage of transistors in off-state. The apparatus for controlling a voltage used in a semiconductor memory device includes...
7580309 Memory refresh method and system  
A memory refresh method applicable in a system memory is disclosed. The memory system comprises a plurality of memory ranks. It is to determine whether an access request corresponds to the memory...
7580308 Semiconductor memory device and refresh method for the same  
A refresh method for a semiconductor memory device features high noise resistance, lower power consumption, and lower cost. All word lines of one or more memory cell blocks that have not been...
7580307 Semiconductor memory device  
An apparatus a counter, storage units for storing count values interrupted by a row address whose refresh period is subject to change; comparator circuits for comparing the counter outputs and the...
7580277 Memory device including a programmable resistance element  
Disclosed are a phase change memory with improved retention characteristic of a phase change device, and a method for refreshing the phase change memory. The fact that a memory is a DRAM interface...
7577025 Semiconductor memory device comprising floating body memory cells and related methods of operation  
A semiconductor device comprising floating body memory cells performs read and write operations by selectively connecting bit lines and inverted bit lines to sense bit lines and inverted sense bit...
7573773 Flash memory with data refresh triggered by controlled scrub data reads  
The quality of data stored in individual blocks of memory cells of a flash memory system is monitored by a scrub read of only a small portion of a block, performed after data are read from less...
7573772 Semiconductor memory device and self-refresh method therefor  
A semiconductor memory device and a self-refresh method in which the semiconductor memory device includes a plurality of input/output ports having respective independent operation, a period of...
7573771 High voltage generator and semiconductor memory device  
A high voltage generator includes: a high voltage detecting unit for detecting a level of a high voltage and outputting a high enable signal; an auto refresh control unit for enabling an auto...
7573751 Flash memory device having single page buffer structure  
A flash memory device includes memory cells, a common node, a sense node connected to a selected bit line, a first register connected to the common node, a second register connected to the common...
7570536 Column redundancy circuit  
A column redundancy circuit is disclosed. The column redundancy circuit includes a first control signal generator configured to receive a refresh flag signal having an enable width larger than that...
7570535 Semiconductor integrated circuit device having memory macros and logic cores on board  
A semiconductor integrated circuit device has memory macros and logic cores. The memory macro is composed of a dynamic memory including an access port and a refresh port. The semiconductor...
7567477 Bias sensing in sense amplifiers through a voltage-coupling/decoupling device  
Voltage coupling/decoupling devices are provided within DRAM devices for improving the bias sensing of sense amplifiers and thus the refresh performance. The voltage coupling/decoupling devices...
7564731 Software refreshed memory device and method  
A software refreshed memory device comprises a plurality of memory cells that must be periodically refreshed to avoid losing data. Preferably, the memory cells can avoid losing data even though the...
7564730 Memory  
A memory includes an access control portion performing an internal access operation on the basis of an external access operation, a refresh control portion performing a refresh operation, a refresh...
7561465 Methods and systems for recovering data in a nonvolatile memory array  
One embodiment of the invention relates to a method for refreshing a nonvolatile memory array. In the method, a threshold voltage of a multi-bit memory cell is analyzed to determine if it has...
7558149 Method and apparatus to control sensing time for nonvolatile memory  
One or more clock signals are used to control sense amplifier measurements. For example, multiple threshold voltage measurement types characterize the multiple clock signals, and selecting the...
7558142 Method and system for controlling refresh to avoid memory cell data losses  
A DRAM includes a register storing subsets of row addresses corresponding to rows containing at least one memory cell that is unable to store a data bit during a normal refresh cycle. Each subset...
7557665 Temperature tracking oscillator circuit  
A temperature-dependent oscillator includes a first current source, wherein a first current provided by the first current source has a positive temperature coefficient, a second current source...