Matches 1 - 50 out of 602 1 2 3 4 5 6 7 8 9 10 11 12 13 >
Match Document Document Title
7616518 Multi-port memory device with serial input/output interface  
A multi-port memory device includes a plurality of ports located at a center region of the multi-port memory device, each for performing a data communication with a corresponding external device; a...
7583557 Multi-port memory device with serial input/output interface and control method thereof  
A semiconductor memory device includes plural ports for transmitting an input data serial-interfaced with an external device into a global data bus, plural banks for parallel-interfacing with the...
7573779 Semiconductor memory and electronic device  
A semiconductor memory that reduces the power consumption of a memory cell array without exercising control by a microprocessor. The semiconductor memory comprises a memory cell array, a switch for...
7573770 Distributed front-end FIFO for source-synchronized interfaces with non-continuous clocks  
In one embodiment of the invention, an integrated circuit, such as an FPGA, comprises a distributed FIFO architecture that supports data transfer from an external device, such as an SDRAM, via an...
7570534 Enqueue event first-in, first-out buffer (FIFO)  
In one embodiment, an apparatus comprises a queue, write control logic coupled to the queue and operable in a write clock domain, and a first-in, first-out buffer (FIFO) coupled to the write...
7567476 Semiconductor memory device and testing method thereof  
A semiconductor memory device includes mini arrays and a serial-parallel conversion circuit. The serial-parallel conversion circuit simultaneously writes two continuous data into mutually different...
7558133 System and method for capturing data signals using a data strobe signal  
A signal capture system and method is used to capture a data signal using a data strobe signal having a preamble of strobe signal transitions. The system includes a data latch circuit receiving the...
7545663 Semiconductor storage device  
Data transfer speed is increased in a semiconductor storage device in which the core unit and the interface unit are separate chips. The device has a plurality of core chips through in which a...
7542365 Apparatus and method for accessing a synchronous serial memory having unknown address bit field size  
An apparatus and method are provided for accessing a serial memory without knowing the required number of address bits. The apparatus comprises a pull circuit, a data out control circuit and a...
7539071 Semiconductor device with a relief processing portion  
Each of a plurality of redundant memories includes a plurality of memory cells and is operable to be relieved when a defective cell exists. This plurality of redundant memories can operate...
7525871 Semiconductor integrated circuit  
Fuse data is supplied to each of a plurality of function blocks through a transfer path using shift registers. When the reliability of fuse elements is low, there is a possibility that a part of...
7523232 Mark/re-read and mark/re-write operations in a multi-queue first-in first-out memory system  
In a multi-queue memory system, a plurality of read count pointers (one for each queue) are stored in a read address file, and used to generate empty flags. A read count pointer associated with a...
7522470 Semiconductor memory device  
When the input write data is a value of a value greater than the existing data of the memory array 100 , the semiconductor memory device enables writing of input write data to the memory array ...
7519789 Method and system for dynamically selecting a clock edge for read data recovery  
A method for dynamically selecting a clock edge for recovering read data received from a slave at a master is provided that includes determining whether an internal clock signal is high when a...
7489567 FIFO memory device with non-volatile storage stage  
A FIFO memory device ( 300 ) comprises a storage device ( 321 ) which is a non-volatile FIFO comprising a plurality of non-volatile storage elements or latches. The FIFO memory device ( 300 ) also...
7489565 Flash memory device including multi-buffer block  
A flash memory device includes a memory cell array and a multi-buffer block which temporarily stores program data that are to be stored in the memory cell array, wherein the multi-buffer block...
7477553 Control device for controlling a buffer memory  
A control device is provided for controlling a buffer memory that can store n data words and is capable of being used for data transfer between a first system and a second system. The control...
7463538 Semiconductor memory device having a precharge control circuit for reducing current during continuous write operation  
We describe a semiconductor memory device having a precharge control circuit and an associated method for precharging the same. A semiconductor memory device having a series of circuits for writing...
7460383 Storage apparatus, controller and control method  
Proposed is a highly reliable storage apparatus with fast access speed and low power consumption, as well as a controller and control method for controlling such a storage apparatus. This storage...
7457188 Semiconductor memory device having connected bit lines and data shift method thereof  
Provided is a semiconductor memory device having connected bit lines and a data shifting method thereof. An embodiment of the semiconductor memory device includes a plurality of memory cell blocks...
7457172 Memory device and method having data path with multiple prefetch I/O configurations  
A memory device is operable in either a high mode or a low speed mode. In either mode, 32 bits of data from each of two memory arrays are prefetched into respective sets of 32 flip-flops. In the...
7457146 Memory cell programmed using a temperature controlled set pulse  
A memory device includes a phase change memory cell and a circuit. The circuit is for programming the memory cell to a selected one of more than two states by applying a temperature controlled set...
7443762 Synchronization circuit for a write operation on a semiconductor memory  
A synchronization circuit for handling and synchronizing a write operation on a semiconductor memory, in which a write operation contains a plurality of write commands, comprises a controllable...
7440351 Wide window clock scheme for loading output FIFO registers  
A circuit provides the widest possible window for capturing data and preventing run-through in a FIFO register. The FIFO register includes two registers per I/O. Two FIFO input clocks are used, one...
7436726 Circuit for and method of reading data in an asynchronous FIFO including a backup address circuit for re-reading data  
A circuit for enabling reading data in an asynchronous FIFO memory of an integrated circuit is described. The circuit comprises a memory storing data in a plurality of slots having a corresponding...
7436725 Data generator having stable duration from trigger arrival to data output start  
A data generator has stable duration from trigger arrival to substantial data output start. A memory provides parallel data according to a divided clock. An address counter provides the same...
7420869 Memory device, use thereof and method for synchronizing a data word  
The invention includes a memory device with a register device to which an output of a multiplexer is connected. The input of the multiplexer is connected to a buffer store. In addition, the memory...
7397727 Write burst stop function in low power DDR sDRAM  
A write burst stop command function is provided for a semiconductor memory device, and in particular for a memory device having a write latency, such as is common in a low power double data rate...
7397717 Serial peripheral interface memory device with an accelerated parallel mode  
A serial peripheral flash memory device uses a plurality of dummy input/output terminals to enable the selection of a parallel mode for devices that have a slower serial clock speed. In parallel...
7397684 Semiconductor memory array with serial control/address bus  
A semiconductor memory array for operation in a data storage system with at least one semiconductor memory chip for the storage of user data and one memory controller for control of the at least...
7394715 Memory system comprising memories with different capacities and storing and reading method thereof  
A memory system includes a first memory, a second memory, a determining unit, and an accessing unit. The capacity of the second memory is different from the capacity of the first memory. The first...
7394710 Auto-recovery fault tolerant memory synchronization  
Automatic fault recovery of upsets in a memory controller are provided to minimize data loss. In addition to memory control, the present invention allows for the incorporation of majority voting...
7382637 Block-writable content addressable memory device  
A content addressable memory device including a memory to store a searchable database, a search circuit, and a first-in-first-out storage circuit. The search circuit generates a plurality of...
7379383 Methods of DDR receiver read re-synchronization  
A method for reading data is provided. The method includes generating two or more pulses from a first clock signal by which the data to be read is received, using each generated pulse to latch data...
7376041 Semiconductor memory device and data read and write method of the same  
A semiconductor memory device includes a memory cell array to store data; a data input portion to output data to the memory cell array in response to a write control signal; a data output portion...
7376021 Data output circuit and method in DDR synchronous semiconductor device  
Embodiments of the present invention include a data output circuit that can read data in parallel from a plurality of latches in a pipeline circuit. Even-numbered data and odd-numbered data are...
7372755 On-chip storage memory for storing variable data bits  
An improved on-chip storage memory and method for storing variable data bits, the memory including an on-chip storage memory system for storing variable data bits that has a memory for storing data...
7366042 Defective column(s) in a memory device/card is/are skipped while serial data programming is performed  
A semiconductor device includes an interface which executes an interfacing process with a semiconductor memory, and a circuit which performs control to write serial data to the semiconductor memory...
7355917 Two-dimensional data memory  
A two-dimensional data memory ( 1 ) comprising memory elements which are arranged in rows and columns, which are designed to store in each case one data word, which in the row direction and in the...
7355878 Programmable logic devices optionally convertible to one time programmable devices  
Programmable logic devices (PLDs) that can be repeatedly erased and reprogrammed, e.g., during the testing and/or design phases, and then converted to one-time programmable (OTP) devices on a...
7353356 High speed, low current consumption FIFO circuit  
A FIFO circuit includes a write counter circuit, a memory circuit, a read counter circuit and a selector circuit. The write counter circuit counts a write clock signal during a valid period of...
7352648 Semiconductor memory  
At least one complete cell array having a predetermined memory capacity and an incomplete cell array having a capacity smaller than the predetermined memory capacity are arranged in one direction....
7340664 Single engine turbo decoder with single frame size buffer for interleaving/deinterleaving  
A method and apparatus for decoding and de-interleaving a received encoded and interleaved signal, the method employing and the apparatus including a single decoder coupled to a common buffer, the...
7321520 Configurable length first-in first-out memory  
A configurable length first-in first-out (FIFO) memory includes a memory core for storing data, a write address counter connected to the memory core for counting locations for writing the data to...
7315479 Redundant memory incorporating serially-connected relief information storage  
A relief processing section which performs a relief process with respect to a redundant memory comprises a plurality of defect relief sections each having shift register circuits (relief...
7313639 Memory system and device with serialized data transfer  
A memory system with serialized data transfer. The memory system includes within a memory controller and a plurality of memory devices. The memory controller receives a plurality of write data...
7304909 Control unit for deactivating and activating the control signals  
A control unit is set up to generate and output periodic clock signals, that are in sync with and at the same frequency as a periodic basic clock that is input into it, and periodic control...
7263019 Serial presence detect functionality on memory component  
Methods and apparatus for accessing serial presence detect data are provided. For some embodiments, serial presence detect logic is incorporated in memory devices, eliminating the need for a...
7260008 Asynchronous first-in-first-out cell  
The present invention discloses an asynchronous first-in-first-out cell, wherein modified Muller C elements are used to reduce the complexity of the circuit of the asynchronous first-in-first-out...
7254079 Electrical fuse circuit  
An electrical fuse circuit of the present invention includes a plurality of electrical fuse cores ( 1 ) each of which has an electrical fuse element ( 3 ) and a switch transistor ( 4 ) connected in...
Matches 1 - 50 out of 602 1 2 3 4 5 6 7 8 9 10 11 12 13 >