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8179728 Interleaving charge pumps for programmable memories  
Systems and methods, including computer software for performing operations enable interleaving of charging operations in a charging pump. A first charge pump is charged to a predetermined level,...
8179737 Semiconductor memory apparatus  
A semiconductor memory apparatus includes an internal circuit configured to be driven by current flowing between first and second voltage nodes, and a current control unit configured to control an...
8154906 Memory cells, memory cell programming methods, memory cell reading methods, memory cell operating methods, and memory devices  
Embodiments disclosed include memory cell operating methods, memory cell programming methods, memory cell reading methods, memory cells, and memory devices. In one embodiment, a memory cell...
8130539 Phase change memory device  
A phase change memory device includes a signal generator configured to generate first and second sensing and amplifying enable signals which are sequentially activated during an activation period...
8130584 Semiconductor device and control method of the same  
The present invention provides a semiconductor memory and a control method therefor, the semiconductor device including a first current-voltage conversion circuit (16) connected to a core cell (12)...
8111570 Devices and methods for a threshold voltage difference compensated sense amplifier  
Embodiments are described for a voltage compensated sense amplifier. One such sense amplifier includes a pair of digit line nodes respectively coupled to a pair of transistors. A first pair of...
8077527 SRAM leakage reduction circuit  
A method and system are provided for maintaining a virtual ground node of an SRAM memory array at a minimum level sufficient for maintaining data retention. A circuit can maintain the virtual...
8068366 Analog read and write paths in a solid state memory device  
A memory array in a memory device is coupled to an analog I/O data interface that enables analog voltage levels to be written to the memory array. The I/O interface comprises a plurality of analog...
8064270 Semiconductor integrated circuit device  
A semiconductor integrated circuit device includes a data circuit and a group of bit line application voltage terminals to which different voltages are applied. The data circuit holds program data...
8044816 Apparatus, system, and method for detecting the formation of a short between a magnetoresistive head and a head substrate  
An apparatus, system, and method are disclosed for detecting the formation of a short between a magnetoresistive (“MR”) head and a head substrate. The apparatus is presented with a logic unit con...
8045390 Memory system with dynamic reference cell and method of operating the same  
A system for operating a memory device includes a memory array having a number of memory cells and a set of dynamic reference cells coupled to the memory cells in word lines. Each of the dynamic...
8031527 Semiconductor device and method for adjusting reference levels of reference cells  
A semiconductor device includes a first reference cell used for programming or reading non-volatile memory cells, and an adjustment circuit adjusting a first reference level of the first reference...
8023313 Resistance change memory device  
A resistance change memory device includes a cell array having multiple layers of mats laminated thereon, each of the mats having word lines and bit lines intersecting each other as well as...
7995408 Circuit for supplying a reference voltage in a semiconductor memory device for testing an internal voltage generator therein  
A reference voltage supplying circuit can include an internal reference voltage generating unit configured to generate an internal reference voltage, a pad configured to receive an external...
7990756 Semiconductor memory device and method for manufacturing same  
Disclosed herein is a semiconductor memory device including a plurality of memory cells including first and second inverters each having first and second driver transistors and first and second...
7986568 Interleaving charge pumps for programmable memories  
Systems and methods, including computer software for performing operations enable interleaving of charging operations in a charging pump. A first charge pump is charged to a predetermined level,...
7983089 Sense amplifier with capacitance-coupled differential sense amplifier  
During first portion of a first read cycle determining that a first input of a sense amplifier is to receive information based upon a state of a storage cell during a first portion of a read cycle,...
7978503 Static semiconductor memory with a dummy call and a write assist operation  
A dummy memory cell for detection of write completion timing is provided as a replica of a memory cell. When assisting a write operation by power supply control and substrate potential control of...
7978556 On-chip temperature sensor  
A temperature invariant reference voltage and a temperature variant physical quantity, such as a voltage or current, are generated. The temperature variant physical quantity changes in response to...
7974134 Voltage generator to compensate sense amplifier trip point over temperature in non-volatile memory  
In a non-volatile memory system, a voltage generator provides a voltage to a gate of a voltage-setting transistor which is used in a sense circuit to set an initial voltage at a sense node. At the...
7957205 Semiconductor device and control method of the same  
The present invention is a semiconductor device including: a resistor R11 (first resistor part) and an FET 15 (second resistor part) connected in series between a power supply Vcc (first power...
7940594 Method and apparatus for increasing yield in a memory device  
An electronic circuit includes multiple circuit elements arranged into multiple distinct subdivisions, each subdivision having a separate voltage supply connection for conveying power to the...
7936615 Methods for supplying power supply voltages in semiconductor memory devices and semiconductor memory devices using the same  
In a method for supplying power supply voltages in a semiconductor memory device a first source voltage is applied to a memory cell of a memory cell array as a cell array internal voltage for...
7924587 Programming of analog memory cells using a single programming pulse per state transition  
A method for data storage in analog memory cells includes defining multiple programming states for storing data in the analog memory cells. The programming states represent respective combinations...
7913193 Determining relative amount of usage of data retaining device based on potential of charge storing device  
An integrated circuit and a design structure are disclosed. An integrated circuit may comprise: a data retaining device; a charge storing device coupled to the data retaining device such that a use...
7903488 Bias sensing in DRAM sense amplifiers through voltage-coupling/decoupling device  
Voltage coupling/decoupling devices are provided within DRAM devices for improving the bias sensing of sense amplifiers and thus the refresh performance. The voltage coupling/decoupling devices...
7903477 Pre-charge voltage generation and power saving modes  
A system includes a voltage generator to produce a pre-charge voltage signal for pre-charging one or more signals in a memory circuit. The one or more signals can be data bus lines used to access...
7898874 Memory device  
A nonvolatile memory device contains at least one nonvolatile memory module and an electrical buffer for buffering a supply voltage for the at least one nonvolatile memory module. A microprocessor...
7894287 Semiconductor memory device controlling a voltage supplied to a dummy bit line  
The present invention relates to a semiconductor memory device, and more precisely to a semiconductor memory device which controls the voltage supplied to a dummy bit line and a biasing method. The...
7894279 Semiconductor storage device comprising reference cell discharge operation load reduction  
A semiconductor storage device precharging a bit line pair to a ground potential includes a sense amplifier connected between the bit line pair, a storage cell connected to one of the bit line pair...
7885131 Resistance change semiconductor memory device and method of reading data with a first and second switch circuit  
A semiconductor memory device of the present invention comprises a memory array and a read circuit that reads data of a selected cell. The memory array includes a plurality of memory cells and a...
7869285 Low voltage operation bias current generation circuit  
Devices and systems for generating a bias current with a low minimum voltage, for example, are disclosed. One such device includes a first transistor having a source coupled to a voltage supply, a...
7869292 Dynamic type semiconductor memory device and operation method of the same  
A dynamic type semiconductor memory device includes a sense amplifier connected with a bit line pair to amplify and sense a voltage difference on the bit line pair; a precharge circuit configured...
7869295 Semiconductor memory apparatus  
A semiconductor memory apparatus includes a sense amplifier that receives a driving voltage through a sense amplifier power supply input terminal and detects and amplifies a difference between...
7864593 Method for classifying memory cells in an integrated circuit  
A method for classifying memory cells in an integrated circuit is provided, wherein the integrated circuit has a memory cell field including a plurality of memory cells. The method includes...
7864608 Semiconductor device  
A semiconductor device includes a DRAM cell configured to store a data; and a sense amplifier activated in response to supply of power supply voltages and configured to sense the data stored in the...
7864598 Dynamic random access memory device suppressing need for voltage-boosting current consumption  
In one embodiment, a semiconductor memory device includes a plurality of pairs of bit lines, each of said pairs including a first bit line, a second bit line, a memory cell coupled to said first...
7835208 Multi-level dynamic memory device  
A multi-level dynamic memory device includes a bit line pair that is divided into a main bit line pair and a sub-bit line pair, first and second sense amplifiers that are connected between the main...
7826272 Semiconductor memory device  
The present invention solves a problem of the degradation of the long-term reliability of a conventional semiconductor memory device due to early deterioration of a FET included in a reference cell...
7826293 Devices and methods for a threshold voltage difference compensated sense amplifier  
A voltage compensated sense amplifier includes a pair of digit line nodes respectively coupled to a pair of transistors. A first pair of switches are adapted to cross-couple the gates of the...
7808830 Semiconductor device and method for adjusting reference levels of reference cells  
A semiconductor device includes a first reference cell used for programming or reading non-volatile memory cells, and an adjustment circuit adjusting a first reference level of the first reference...
7791975 Scalable embedded DRAM array  
A method and apparatus for scaling an embedded DRAM array from a first process to a second process, wherein the scaling involves reducing the linear dimensions of features by a constant scale...
7773445 Reading method and circuit for a non-volatile memory device based on the adaptive generation of a reference electrical quantity  
A circuit for determining the value of a datum stored in an array memory cell of a non-volatile memory device having at least one reference memory cell of known content. The circuit has a...
7768813 DRAM with word line compensation  
In one embodiment, a DRAM is provided that includes: a word line intersecting with a pair of bit lines, the DRAM including a memory cell at each intersection, each memory cell including an access...
7768812 Memory cells, memory cell programming methods, memory cell reading methods, memory cell operating methods, and memory devices  
Embodiments disclosed include memory cell operating methods, memory cell programming methods, memory cell reading methods, memory cells, and memory devices. In one embodiment, a memory cell...
7768832 Analog read and write paths in a solid state memory device  
A memory array in a memory device is coupled to an analog I/O data interface that enables analog voltage levels to be written to the memory array. The I/O interface is comprised of a plurality of...
7755964 Memory device with configurable delay tracking  
A memory device with configurable delay tracking is described. The memory device includes M normal word line drivers, a dummy word line driver a memory array, N sense amplifiers, and a timing...
7742354 Random access memory data resetting method  
A random access memory data resetting method is provided. The method includes following steps. First, a state machine resetting signal is provided to a RAM. Next, the state machine resetting signal...
7738305 Read-out circuit for or in a ROM memory; ROM memory and method for reading the ROM memory  
A read-out circuit for or in a ROM memory, comprises an input, a comparator circuit, a threshold setting, and a control signal generator for driving the threshold setting generator. A read signal...
7733724 Controlling global bit line pre-charge time for high speed eDRAM  
A method of operating a memory includes performing a write operation and a read operation on a memory cell. The write operation includes starting a first global bit line (GBL) pre-charge on a GBL;...
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