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8164934 Content addressable memory  
An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a...
8159891 Sensing characteristic evaluating apparatus for semiconductor device and method thereof  
A sensing characteristic evaluating apparatus for a semiconductor device includes a test current supply unit configured to supply a test current to an input/output line during a test mode for...
8159869 Circuit and method for generating reference voltage, phase change random access memory apparatus and read method using the same  
A circuit for generating a reference voltage includes at least one reference cell, a reference cell write driver, a reference cell sense amplifier, and a voltage compensation unit. The reference...
8154917 Magnetic storage device  
A magnetic storage device includes a plurality of MRAM memory cells connected to a data transfer line, a clamp transistor connected between the data transfer line and a reading signal line and...
8149627 Current sink system based on sample and hold for source side sensing  
Source-side sensing techniques described herein determine the data value stored in a memory cell based on the difference in current between the read current from the source terminal of the memory...
8144541 Method and apparatus for adjusting and obtaining a reference voltage  
A method for adjusting a reference voltage is provided, including: decoding a default code configured in a reference voltage register in a chip to obtain an actual reference voltage; comparing the...
8144500 Semiconductor memory device  
According to one embodiment, semiconductor memory device includes: semiconductor substrate; parallel first lines stacked on substrate; parallel second lines intersecting first lines; memory cell...
8144538 Semiconductor device  
A semiconductor device to improve layout uniformity may include an active region formed in a substrate, a dummy active region formed in the substrate and separated from the active region, a word...
8143653 Variable resistance memory device and system thereof  
A phase-change random access memory device is provided. The phase-change random access memory device includes a global bit line connected to a write circuit and a read circuit, multiple local bit...
8139409 Access signal adjustment circuits and methods for memory cells in a cross-point array  
Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to generate access signals to facilitate...
8134866 Phase change memory devices and systems, and related programming methods  
A method programs a phase change memory device. The method comprises receiving program data for selected memory cells; generating bias voltages based on reference cells; sensing read data stored in...
8134881 Thermally stable reference voltage generator for MRAM  
A non volatile memory device comprises memory cells such as MRAM cells, reading circuits and a reference cell for generating a reference for use by the reading circuits, and can determine if the...
8130539 Phase change memory device  
A phase change memory device includes a signal generator configured to generate first and second sensing and amplifying enable signals which are sequentially activated during an activation period...
8130582 Semiconductor signal processing device  
A unit operator cell includes a plurality of SOI (Silicon on Insulator) transistors, write data is stored in a body region of at least two SOI transistors, and the storage SOI transistors are...
8130584 Semiconductor device and control method of the same  
The present invention provides a semiconductor memory and a control method therefor, the semiconductor device including a first current-voltage conversion circuit (16) connected to a core cell (12)...
8125845 Semiconductor integrated circuit device and operating method thereof  
Even when memory capacity of a memory that uses a replica bit-line is made higher, fluctuations of a generating timing of a sense-amplifier enable signal are reduced. A semiconductor integrated...
8125844 Semiconductor memory device for low voltage  
A semiconductor memory device includes a first cell array including a plurality of unit cells and a bit line sense amplifying unit for sensing and amplifying data signals stored in the unit cells....
8116119 Desensitizing static random access memory (SRAM) to process variations  
A static random access memory (SRAM) can include a plurality of columns forming a memory array, wherein each column comprises a plurality of memory cells coupled to bitlines and wordlines, and a...
8102713 Non-volatile memory monitor  
The invention provides circuits, systems, and methods for monitoring a non-volatile memory (NVM) cell, or an array of NVM cells. The monitor is capable of switching from a normal operating state to...
8093668 Magnetoresistive random access memory including reference cells  
A magnetoresistive random access memory includes first and second magnetoresistive effect element. A shape of the first magnetoresistive effect element has a first length in a first direction and a...
8089812 Semiconductor memory device  
A semiconductor memory device can reduce a circuit area necessary for row repair. The semiconductor memory device includes a plurality of memory banks, a plurality of cell arrays arranged in each...
8089811 Flash memory devices with memory cells strings including dummy transistors with selective threshold voltages  
Flash memory devices include a first memory cell string including a plurality of serially-connected memory cells and first and second serially-connected dummy transistors configured to couple the...
8085573 Ferroelectric memory  
A ferroelectric memory of an embodiment of the present invention includes a plurality of units, in each of which a ferroelectric capacitor and a transistor are connected to each other in parallel....
8085611 Twisted data lines to avoid over-erase cell result coupling to normal cell result  
Over-erasure induced noise on a data line in a nonvolatile memory that couples into an adjacent data line is mitigated by using twisted data lines and differential sensing amplifiers. Noise coupled...
8077493 Semiconductor memory device  
A semiconductor memory device includes a memory cell array disposing a plurality of memory cells at each intersection of word lines and bit lines, the memory cell including one pair of...
8068367 Reference current sources  
Systems, methods, and devices are disclosed, including an electronic device that includes a first data location, a quantizing circuit, and a reference current source, all coupled to an electrical...
8064262 Semiconductor device and method using stress information  
A semiconductor device in accordance with one embodiment of the invention can include a first data storage region including a non-volatile main data storage region. Additionally, the semiconductor...
8059481 Semiconductor memory device  
A semiconductor memory device includes a memory cell array provided with a main memory cell array including a plurality of memory cells, and a dummy column including a plurality of dummy memory...
8059480 Semiconductor memory device  
A semiconductor memory device includes a plurality of memory cells configured to correspond to each of a plurality of word lines for storing data; a plurality of reference memory cells configured...
8054668 Method and apparatus for storing data in a write-once non-volatile memory  
In an illustrative embodiment, a memory cell comprises a first and a second MOSFET, wherein the first MOSFET undergoes a process to modify the threshold voltage such that a modified threshold...
8051342 Semiconductor memory device  
A semiconductor memory device including: a memory cell array including a plurality of word lines, a plurality of bit lines, and memory cells arranged in portions where the plurality of word lines...
8045389 Semiconductor memory device  
A dummy cell array is provided in a memory cell array, and an intermediate buffer is provided between input/output circuits, whereby control signals to the input/output circuits can be operated at...
8045388 Semiconductor device and control method of the same  
The present invention provides a semiconductor memory and a control method therefor, the semiconductor device including a first current-voltage conversion circuit (16) connected to a core cell (12)...
8045390 Memory system with dynamic reference cell and method of operating the same  
A system for operating a memory device includes a memory array having a number of memory cells and a set of dynamic reference cells coupled to the memory cells in word lines. Each of the dynamic...
8040746 Efficient word lines, bit line and precharge tracking in self-timed memory device  
A memory device for efficient word line, bit line and precharge tracking is provided. The memory device includes a memory array, one or more address decoders, a word line driver, a plurality of...
8040744 Spare block management of non-volatile memories  
Techniques for the management of spare blocks in re-programmable non-volatile memory system, such as a flash EEPROM system, are presented. In one set of techniques, for a memory partitioned into...
8040734 Current-mode sense amplifying method  
A sense amplifying method, applied in a memory having a memory cell and a reference cell, includes: charging the memory cell and the reference cell to have a cell current and a reference current,...
8031527 Semiconductor device and method for adjusting reference levels of reference cells  
A semiconductor device includes a first reference cell used for programming or reading non-volatile memory cells, and an adjustment circuit adjusting a first reference level of the first reference...
8031529 Memory cell threshold voltage drift estimation methods and apparatus  
Methods of operating memory devices include determining a threshold voltage drift of two or more reference memory cells of the memory device programmed to only a subset of data states of the memory...
8027206 Bit line voltage control in spin transfer torque magnetoresistive random access memory  
A Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) and associated read operations are disclosed. A bit cell includes a magnetic tunnel junction (MTJ) and a word line...
8023352 Semiconductor storage device  
In a 4F2 memory cell designed using an SGT as a vertical transistor, a bit line has a high resistance because it is comprised of a diffusion layer underneath a pillar-shaped silicon layer, which...
8023311 Resistive memory devices including selected reference memory cells operating responsive to read operations  
A Resistance based Random Access Memory (ReRAM) can include a sense amplifier circuit that includes a first input coupled to a bit line of a reference cell in a first block of the ReRAM responsive...
8014202 Non-volatile semiconductor memory device  
In a non-volatile semiconductor memory device, variations in voltage applied to a bit line when an erase voltage applying step is repeatedly executed are suppressed, thereby reducing variations in...
8014221 Memory devices including floating body transistor capacitorless memory cells and related methods  
A semiconductor memory device includes a memory cell array which includes a plurality of unit memory cells, where each of the unit memory cells comprises complementary first and second floating...
8014194 Phase change memory  
A phase change memory (PCM) in which the phase change storage element is crystallized by a gradually increasing/decreasing operating current. The PCM comprises a switching circuit, the phase change...
8009488 Semiconductor memory device  
A semiconductor memory device includes a plurality of memory cell array blocks connected to word lines, source lines, and bit lines, each memory cell array including memory cells each having a...
8004880 Read disturb reduction circuit for spin transfer torque magnetoresistive random access memory  
Systems, circuits and methods for reducing read disturbances in Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) are disclosed. A resistive element can be used during the read...
8000133 Thin film magnetic memory device capable of conducting stable data read and write operations  
A tunnel magnetic resistive element forming a magnetic memory cell includes a fixed magnetic layer having a fixed magnetic field of a fixed direction, a free magnetic layer magnetized by an applied...
7995412 Analog-to-digital and digital-to-analog conversion window adjustment based on reference cells in a memory device  
An analog-to-digital conversion window is defined by reference voltages stored in reference memory cells of a memory device. A first reference voltage is read to define an upper limit of the...
7995379 Semiconductor memory device  
A semiconductor memory device includes a sense amplifier that compares intensities of currents flowing through a first node and a second node with each other, a first MOSFET having a drain terminal...
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