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7616513 Memory device, current sense amplifier, and method of operating the same  
A memory device, current sense amplifier and method of operating the same are disclosed herein. In accordance with one embodiment, the current sense amplifier circuit may include a pair of...
7616512 Semiconductor memory device with hierarchical bit line structure  
A semiconductor memory device has a hierarchical bit line structure. The semiconductor memory device may include first and second memory cell clusters, which share the same bit line pair and are...
7616511 Input/output line sense amplifier and semiconductor memory device using the same  
An input/output (I/O) line sense amplifier includes a buffer unit, a sense amplifier, and a precharge unit. The buffer unit is driven by a first level voltage to buffer a strobe signal, and the...
7613057 Circuit and method for a sense amplifier  
A circuit and method for providing a sense amplifier for a DRAM memory with reduced distortion in a control signal, the sense amplifier particularly useful for embedding DRAM memory with other...
7613047 Efficient circuit and method to measure resistance thresholds  
The embodiments of the invention provide an apparatus, method, etc. for an efficient circuit and method to measure resistance. A sense line driver for an integrated circuit memory is provided,...
7613038 Semiconductor integrated circuit device  
There is achieved a high-integrated and high-speed nonvolatile memory which can stabilize an operation of a phase-change memory for a short operation cycle time. A latch is provided in a write...
7613024 Local digit line architecture and method for memory devices having multi-bit or low capacitance memory cells  
A DRAM array includes for each column a pair of complimentary digit lines that are coupled to a sense amplifier. Each of the global digit lines is selectively coupled to a plurality of local digit...
7609577 Design structure for improving sensing margin of electrically programmable fuses  
A design structure embodied in a machine readable medium used in a design process includes an apparatus for sensing the state of a programmable resistive memory element device, the apparatus...
7609573 Embedded memory databus architecture  
A dynamic random access memory (DRAM) having pairs of bitlines, each pair being connected to a first bit line sense amplifier, wordlines crossing the bitlines pairs forming an array, charge storage...
7609572 Semiconductor memory device  
In a semiconductor memory device, with respect to low voltage application, technique of controlling a gate voltage of a shared MOS transistor increasing sense speed and increasing data read speed...
7609571 Semiconductor memory device having a control unit receiving a sensing block selection address signal and related method  
Embodiments of the invention include a semiconductor memory device and a method for operating the semiconductor memory device. The invention includes a semiconductor memory device comprising a...
7609570 Switched capacitor charge sharing technique for integrated circuit devices enabling signal generation of disparate selected signal values  
A switched capacitor charge sharing technique for integrated circuit devices which allows for efficient charge sharing and signal level generation of exact desired values, and wherein the signal...
7609568 Method and device for securing an integrated circuit, in particular a microprocessor card  
A method processes parallel electrical signals, using parallel processing circuits that process successive cycles of electrical signals according to a rule for allocating electrical signals to the...
7606097 Array sense amplifiers, memory devices and systems including same, and methods of operation  
A sense amplifier having an amplifier stage with decreased gain is described. The sense amplifier includes a first input/output (“I/O”) node and a second complementary I/O node. The sense...
7606096 Semiconductor integrated circuit device  
A semiconductor integrated circuit device, has a first variable resistor element and a second variable resistor element whose resistances are changed complementarily depending on a current; and a...
7606093 Optimized charge sharing for data bus skew applications  
A circuit and method provide a charge sharing function during skewed data bus conditions in an integrated circuit memory. The charge sharing circuit includes two additional circuit blocks, one...
7606087 Semiconductor memory device and over driving method thereof  
A semiconductor memory device may include a power line, an over driver, and/or an internal voltage driver. The power line may be connected to at least one sense amplifier. The at least one sense...
7602657 Semiconductor memory device having floating body cell  
A semiconductor memory device includes a sense amplifier for the FBC, a first node and a second node can be disconnected from each other by a first isolation transistor. A third node and a fourth...
7600071 Circuit having relaxed setup time via reciprocal clock and data gating  
An integrated circuit includes a circuit output, a data input that receives a data signal, and a clock input that receives a clock signal. The integrated circuit further includes first and second...
7599238 Semiconductor memory device and driving method thereof  
A semiconductor memory device, for performing a writing operation faster without expanding a driver for the writing operation, includes a bit line sense amplifier (BLSA) for sensing and amplifying...
7599237 Memory device and method for precharging a memory device  
A memory device having a short precharge time is included. The memory device selects at least two pairs of bit lines and connects the selected two pairs of bit lines to the sense amplifier within a...
7599214 Semiconductor memory device  
Source contacts of driver transistors are short-circuited through the use of an internal metal line within a memory cell. This metal line is isolated from memory cells in an adjacent column and...
7599212 Method and apparatus for high-efficiency operation of a dynamic random access memory  
The disclosure generally relates to a method and apparatus for reading and writing information to a memory cell in communication with a word line and one of a bit line or a complementary bit line....
7599167 Active balancing circuit modules, systems and capacitor devices  
Circuit modules, systems and devices for controlling voltages across capacitors.
7596044 Semiconductor memory device having sense amplifier operable as a semi-latch type and a full-latch type based on timing and data sensing method thereof  
A semiconductor memory device includes a memory cell array having memory cells arranged in rows and columns, a row decoder selecting one of the rows and activating the selected row, a bit-line...
7593282 Memory core with single contacts and semiconductor memory device having the same  
A memory core includes a first sub-memory array including a plurality of first memory cells, a second sub-memory array including a plurality of second memory cells, a bit line amplification circuit...
7593277 Method for compensated sensing in non-volatile memory  
One or more sense amplifiers for sensing the conduction current of non-volatile memory is controlled by signals that are timed by a reference sense amplifier having similar characteristics and...
7590018 Sense amp circuit, and semiconductor memory device using the same  
A differential input circuit receives differential input signals at a pair of differential input terminals and produces a pair of first differential output signals. A sensing circuit senses at...
7590017 DRAM bitline precharge scheme  
Circuits and method for precharging a pair of complementary bitlines in a dynamic random access memory (DRAM). Both bitlines are precharged to VDD during a precharge phase, and during a sensing...
7590010 Data output circuit in semiconductor memory device  
A data output circuit includes a sense amplifier and first and second latches. The sense amplifier is for amplifying differential data to generate amplified differential data. The first latch is...
7589991 Semiconductor memory device  
A storage node voltage control circuit is added to a memory cell including two load transistors, two drive transistors and two access transistors. The storage node voltage control circuit performs...
7586803 Semiconductor memory device with reduced sense amplification time and operation method thereof  
A semiconductor memory device is capable of swiftly sensing data loaded on local I/O lines and transferring the sensed data to a global I/O line, thereby reducing an operating time of a sense...
7586780 Semiconductor memory device  
In a semiconductor memory device including memory cells each having two inverters connected in a cross-coupled configuration to hold High data and Low data as a pair and two access transistors, a...
7583550 Semiconductor memory device  
In a sense amplifier circuit having a plurality of sense amplifier portions arranged in order, each of the sense amplifier portions includes a transistor that supplies a bit line potential to a bit...
7583547 Over-driving circuit in semiconductor memory device  
A semiconductor memory over-driving scheme for a semiconductor memory device makes it possible to secure a high-speed sensing operation of a memory sense amplifier, regardless of a change of a...
7580313 Semiconductor memory device for reducing cell area  
A semiconductor memory device with a reduced cell area and a high-speed data transfer by modifying a circuit layout. The semiconductor memory device includes: a cell area with a first and a second...
7580291 Data register with efficient erase, program verify, and direct bit-line memory access features  
A programmable memory device circuit comprising a sense and programming circuit, a latch circuit, a verify circuit for coupling the latch circuit logic value to a shared indicator line, and a...
7577051 SRAM including reduced swing amplifiers  
SRAM includes reduced swing amplifiers, such that a first reduced swing amplifier serves as a local sense amp for reading a memory cell through a short local bit line, a second reduced swing...
7577046 Circuit and method for generating column path control signals in semiconductor device  
A circuit for generating column path control signals in a semiconductor device is provided. The circuit includes a strobe signal delay unit configured to receive a strobe signal, and delay the...
7573756 Sense amplifiers and semiconductor memory devices for reducing power consumption and methods for operating the same  
In a sense amplifier, a current amplifier outputs a first and a second voltage signal in response to a first control signal. The first and second voltage signals are output based on a detected...
7573755 Data amplifying circuit for semiconductor integrated circuit  
A data amplifying circuit for a semiconductor integrated circuit including a controller configured to generate a control signal for adjusting an amplification step in response to a test signal, and...
7570529 Sense amplifier circuit of semiconductor memory device and method of operating the same  
A sense amplifier circuit of a semiconductor memory device and a method of operating the same, in which the sense amplifier circuit includes a bit line sense amplifier connected with a bit line to...
7570506 Ferroelectric memory device and electronic apparatus  
A ferroelectric memory device includes: a first p-channel type MISFET connected between a first bit line and a first node; a second p-channel type MISFET connected between a second bit line and a...
7567477 Bias sensing in sense amplifiers through a voltage-coupling/decoupling device  
Voltage coupling/decoupling devices are provided within DRAM devices for improving the bias sensing of sense amplifiers and thus the refresh performance. The voltage coupling/decoupling devices...
7567475 Memory architecture  
A memory architecture includes a matrix of memory cells structured into rows and columns and associated with a row decoder, an array of reference cells associated with the matrix, a first detector...
7567452 Multi-level dynamic memory device having open bit line structure and method of driving the same  
A multi-level dynamic memory device having an open bit line structure is disclosed. The multi-level dynamic memory device includes a plurality of word lines; a plurality of bit lines provided in an...
7561486 Flash memory devices with flash fuse cell arrays  
A flash memory device includes a flash cell array, a first flash fuse cell fusing circuit, a second flash fuse cell fusing circuit, a third flash fuse cell fusing circuit and a plurality of fuse...
7561480 Ground biased bitline register file  
In general, in one aspect, the disclosure describes an apparatus including a memory cell. Ground biased write control circuitry is used to bias write and writebar bitlines when the memory cell is...
7561462 Circuit and method for a high speed dynamic RAM  
An architecture, circuit and method for providing a high speed operation DRAM memory with reduced cell disturb. A DRAM global bit line select circuit couples a pair of local bit lines and the...
7558140 Method for using a spatially distributed amplifier circuit  
An exemplary amplifier circuit includes a first group of spatially distributed final amplifier stages having a first configuration, and a second group of spatially distributed final amplifier...
Matches 1 - 50 out of 1679 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >