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8868829 Memory circuit system and method  
A method includes presenting multiple memory circuits to a system as a virtual memory circuit having at least one characteristic that is different from a corresponding characteristic of one of the...
8867291 Semiconductor apparatus  
A semiconductor apparatus including an equalizing unit configured to equalize voltages of a bit line and a bit bar line in response to an equalization signal; a precharge circuit unit configured to...
8867292 Semiconductor device, method of retrieving data, and microcomputer  
A semiconductor device includes a data memory cell for storing data; a reference data memory cell for storing reference data to be compared with the data; an inverted data memory cell for storing...
8861285 Apparatuses and methods for line charge sharing  
Apparatuses and methods for charge sharing between signal lines are disclosed. An example apparatus may include first and second lines and a charge sharing circuit. The charge sharing circuit may...
8861264 Memory device, precharge controlling method thereof, and devices having the same  
A pre-charge controlling method and device are provided. The pre-charge controlling method includes pre-charging a first global bit line with a first pre-charge voltage by using at least a first...
8861300 Non-blocking multi-port memory formed from smaller multi-port memories  
A multi-port memory may be formed from a plurality of “simpler” memories. In one implementation, the memory includes a write port and a number of memories provided in groups, such that the wri...
8854909 Semiconductor memory device and method of testing the same  
A semiconductor memory device including an open bit line structure is disclosed. The semiconductor memory device including an open bit line structure includes a first mat, a second mat contiguous...
8848474 Capacitive coupled sense amplifier biased at maximum gain point  
A sense amplifier includes a first inverter including a first input node and a first output node, the first input node coupled to a first bitline through a first capacitor, the first output node...
8848426 Cross-point variable resistance nonvolatile memory device and reading method for cross-point variable resistance nonvolatile memory device  
A cross-point variable resistance nonvolatile memory device comprises: a memory cell array; a column decoder and pre-charge circuit which pre-charges a selected word line to a first voltage in a...
8842487 Power management domino SRAM bit line discharge circuit  
A domino static random access memory (SRAM) having one or more SRAM memory cells connected with a local bit line is disclosed. The SRAM may include a global bit line, a first precharge device...
8842483 Semiconductor device and method of operating the same  
A semiconductor device and a method of operating the same, the semiconductor device including a sense amplifier connected between a bit line and a complementary bit line; a first power supply...
8842480 Automated control of opening and closing of synchronous dynamic random access memory rows  
An apparatus including a protocol engine and a built-in self test (BIST) engine. The built-in self test (BIST) engine is coupled to the protocol engine. The built-in self test (BIST) engine may be...
8837244 Memory output circuit  
The invention provides a memory output circuit. The memory output circuit is capable of receiving bit line data and bit bar line data output by a memory cell array. In one embodiment, the memory...
8837234 Voltage control method to minimize a coupling noise between adjacent global bit lines during read-while operation and memory device using the same  
A memory device is provided, which includes a plurality of global bit lines, a discharge line, a switching circuit configured to connect the plurality of global bit lines to the discharge line in...
8824230 Method and apparatus of reducing leakage power in multiple port SRAM memory cell  
Systems and method for reducing leakage currents and power consumption in a memory array comprising memory cells, such as 8T SRAM cells. The memory array includes logic for dynamically placing a...
8824231 Reduced noise DRAM sensing  
A dynamic random access memory device is described. A first array has a first plurality of bitlines, each coupled to a column of memory cells. A second has a second plurality of bitlines, each...
8824229 Semiconductor memory apparatus having a pre-discharging function, semiconductor integrated circuit having the same, and method for driving the same  
A semiconductor memory apparatus includes a bit line coupled to a plurality of memory cells, a discharge controller configured to generate a bit line discharge signal to pre-discharge the bit line...
8824238 Memory device with bi-directional tracking of timing constraints  
A memory device includes a DRAM, a first bi-directional tracking circuit and a second bi-directional tracking circuit. The DRAM includes a cell, a word line and a bit line. The first bi-directional...
8824233 Systems, circuits, and methods for charge sharing  
Systems, circuits, and methods are disclosed for charge sharing. In one such example system, a first line is configured to be driven to a first voltage representative of data to be placed on the...
8824232 Semiconductor memory device and method of operating the same  
A semiconductor memory device may include a cell string configured to include memory cells, a page buffer coupled to the cell string through a bit line, and configured to include a latch for...
8824201 Semiconductor memory apparatus and data reading method thereof  
A semiconductor memory apparatus includes: a read current supply unit configured to supply a read current; a resistive memory cell configured to pass a current having a magnitude corresponding to a...
8817562 Devices and methods for controlling memory cell pre-charge operations  
A memory having a memory array having bit cells coupled to bit lines. The memory further includes a precharge circuit that precharges bit lines. The memory also includes a control circuit coupled...
8817554 Sense amplifiers, memories, and apparatuses and methods for sensing a data state of a memory cell  
Sense amplifiers, memories, and apparatuses and methods for sensing a data state of a memory cell are disclosed. An example apparatus includes a differential amplifier configured to amplify a...
8817567 Semiconductor memory device having low power mode and related method of operation  
A semiconductor memory device has a normal power mode and a low power mode. In the low power mode, a selection circuit assigns one data address to at least two memory cells in the semiconductor...
8811104 Semiconductor memory and system  
A semiconductor memory includes a real memory cell; a sense amplifier configured to amplify data read from the real memory cell in response to activation of a sense amplifier enable signal; a...
8811102 Multiple read port memory system with a single port memory cell  
An improved multi-port register file system and method of operating. The multi-port register file memory system comprises: n single memory bit cells each storing a data value and having a single...
8811111 Memory controller with reduced power consumption, memory device, and memory system  
A memory device comprising: at least one bank of memory cells that receives a first clock for clocking commands and a second clock for clocking data, wherein the second clock is activated based on...
8811103 Semiconductor memory integrated device having a precharge circuit with thin-film transistors gated by a voltage higher than a power supply voltage  
Provided is a semiconductor integrated device including a semiconductor memory circuit and a peripheral circuit of the semiconductor memory circuit. The peripheral circuit includes a first...
8804446 Semiconductor device having equalizing circuit equalizing pair of bit lines  
A semiconductor device includes: a sense amplifier including an equalizing circuit that equalizes a pair of bit lines; an equalizing control circuit that converts the amplitude of an equalizing...
8804406 Conditional read-assist feature to accelerate access time in an electronic device  
An electronic storage device includes a bit cell circuit, feedback circuit, and read accelerator circuit. The bit cell circuit is adapted for connection with true and complementary bit lines. The...
8804395 Semiconductor device, control method thereof and data processing system  
Disclosed herein is a semiconductor device comprising a global bit line, a first local bit line coupled to normal memory cells, a second local bit line coupled to redundant memory cells first and...
8797816 Semiconductor memory apparatus and bit line equalizing circuit  
A semiconductor memory apparatus comprises bit line sense amplifier unit, and a pair of precharge elements coupled in series between a first bit line and a second bit line and having an...
8797823 Implementing SDRAM having no RAS to CAS delay in write operation  
A method and circuit for implementing faster-cycle-time and lower-energy write operations for Synchronous Dynamic Random Access Memory (SDRAM), and a design structure on which the subject circuit...
RE45036 Semiconductor memory device  
A semiconductor memory device includes a first first-type well including a first cell array for storing a data to apply the data to one of a first bit line and a first bit line bar, and a first...
8787102 Memory device and signal processing circuit  
A memory device which can keep a stored logic state even when the power is off is provided. A signal processing circuit including the memory device, which achieves low power consumption by stopping...
8787059 Cascaded content addressable memory array having multiple row segment activation  
A content addressable memory (CAM) device has an array including a plurality of CAM rows that are partitioned into row segments, wherein a respective row includes a first row segment including a...
8780658 Leakage reduction in memory devices  
A memory device includes a core array that includes memory cells. The memory device also includes a headswitch coupled to the core array and a positive supply voltage. The headswitch reduces...
8773924 Read assist scheme for reducing read access time in a memory  
A read circuit includes a precharge circuit, coupled with at least a subset of bit lines and a sense circuit in a memory, and a transmission gate. The precharge circuit receives a first control...
8773933 Techniques for accessing memory cells  
Techniques for accessing memory cells are disclosed. In one particular embodiment, the techniques may be realized as an apparatus providing voltage to a high impedance node of a memory cell. The...
8767503 Clock transfer circuit and semiconductor device including the same  
A clock transfer circuit includes a clock transfer unit configured to receive an external clock and transfer the received external clock as one or more internal clocks and a clock control unit...
8767494 Far end resistance tracking design with near end pre-charge control for faster recovery time  
A wordline tracking circuit and corresponding method are disclosed, and include a tracking wordline having an impedance characteristic associated therewith that models a row of memory cells in a...
RE44978 Method of verifying programming of a nonvolatile memory device  
A first verify voltage is applied to a word line of a selected memory cell, after a bit line is precharged, to program-verify the memory cell in a nonvolatile memory device. A first read evaluation...
8767492 Methods and systems to read register files with un-clocked read wordlines and clocked bitlines, and to pre-charge a biteline to a configurable voltage  
A method and system to improve the operations of a memory device by reducing its bit line leakage, power consumption, and read access time. The memory device has a static read word line for each of...
8767493 SRAM differential voltage sensing apparatus  
An SRAM differential voltage sensing apparatus is coupled to a memory circuit. The memory circuit comprises a memory bank, a plurality of bit lines, a plurality of data lines coupled to the...
8760951 Method of reading data in a non-volatile memory device  
A method of reading data in a non-volatile memory device compensates for a change in a reading/verifying result in accordance with a change of temperature. The method includes sensing a temperature...
8755217 Semiconductor memory device  
A semiconductor memory device includes a memory cell connected to a read bit line and a pair of write bit lines, and a data amplifier connected to the read bit line. A precharge potential resetting...
8755234 Temperature based compensation during verify operations for non-volatile storage  
A non-volatile storage system that performs programming and reading processes. The programming process includes coarse/fine programming and verify operations. Programming is verified by testing for...
8750054 Data input/output circuit and semiconductor memory device  
A data input/output circuit includes: an amplification unit configured to generate a data signal by amplifying data of a first input/output line coupled to a bank during a read operation, and...
8750063 Sense amplifier control circuit and semiconductor memory device including the same  
A sense amplifier control circuit according to the present invention is disposed in a bit line sense amplifier (BLSA) array region including a plurality of BLSAs and is configured to supply a...
8743639 Semiconductor memory device  
A semiconductor memory device includes a switching unit coupled between a local sense amplifier and a bit line sense amplifier and configured to be turned on in response to a switching signal which...