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8971131 Data circuit  
A circuit includes a first plurality of memory cells coupled with a first data line and a first data transfer circuit coupled with the first data line and a second data line. In a first operation...
8971141 Compact high speed sense amplifier for non-volatile memory and hybrid lockout  
A compact and versatile high speed sense amplifier suitable for use in non-volatile memory circuits is presented. The sense amp circuit uses one power supply level for the bit line driving path and...
8971140 Semiconductor device and data processing system comprising semiconductor device  
A semiconductor device comprises a sense amplifier circuit amplifying a signal transmitted through the bit line, first/second data lines transmitting the signal amplified by the sense amplifier...
8964445 Ferroelectric random access memory with isolated power supply during write and write-back cycles  
In an embodiment of the invention, a method is provided for isolating a ferroelectric memory from a power supply during a write-back cycle or a write cycle of the ferroelectric memory. After it is...
8964496 Apparatuses and methods for performing compare operations using sensing circuitry  
The present disclosure includes apparatuses and methods related to performing compare and/or report operations using sensing circuitry. An example method can include charging an input/output (IO)...
8964449 Semiconductor memory device  
A semiconductor memory device selects one of a plurality of memory cells as a dummy memory cell. The dummy memory cell is connected to a bit line that is complementary to a bit line connected to a...
8964439 Semiconductor device having hierarchical bit line structure  
A semiconductor device comprises first and second global bit lines, a sense amplifier amplifying a voltage difference of the first and second global bit lines, first and second local bit lines...
8958254 High performance two-port SRAM architecture using 8T high performance single port bit cell  
An 8T memory bit cell receives a clock signal and read and write address signals. A read address latch/clock circuit receives the clock signal and the read address signals and initiates a read...
8953401 Memory device and method for driving memory array thereof  
A memory array includes a plurality of columns of memory cells and each column of memory cells of the memory array is coupled to a local voltage source, a bit line, and a bit line bar. Provide a...
8953399 Differential sense amplifier without dedicated pass-gate transistors  
A differential sense amplifier for sensing data stored in a plurality of memory cells of a memory cell array, including a first CMOS inverter having an output connected to a first bit line and an...
8953400 Data control circuit  
The data control circuit includes an input/output line and a driver. The input/output line precharging circuit precharges a global input/output line to a predetermined voltage when either a reading...
8947967 Shared integrated sleep mode regulator for SRAM memory  
Embodiments are described for a method for regulating sleep mode of a plurality of sub-banks in an SRAM array by isolating all of the sub-banks from a regulator upon access to at least one sub-bank...
8947968 Memory having power saving mode  
A memory has a normal mode and a power saving mode. The memory has bitline precharge circuitry which during the normal mode selectively couples a pair of bitlines to a precharge node to charge the...
8947963 Variable pre-charge levels for improved cell stability  
Embodiments of a memory device are disclosed that may allow for multiple pre-charge voltages. The memory device may include a plurality of data lines, and a plurality of pre-charge circuits. Each...
8947960 Semiconductor storage with a floating detection circuitry and floating detection method thereof  
A storage medium including a plurality of memory cells, a plurality of transmission lines, a driving module and a floating detection module is disclosed. The memory cells store data. The...
8942052 Complementary metal-oxide-semiconductor (CMOS) min/max voltage circuit for switching between multiple voltages  
A voltage selection mechanism is provided for switching between multiple voltages without causing a direct current (DC) that may further stress storage elements due to excessive power consumption...
8942021 Semiconductor device  
A semiconductor device includes: an I/O circuit configured to input/output a data signal; a plurality of internal circuits configured to transmit and receive the data signal to/from the I/O...
8937841 Driver for semiconductor memory and method thereof  
A driver for a semiconductor memory includes: a selection controller configured to output a target charge current select signal and a bucket charge current select signal in response to an inputted...
8934314 Apparatus and method for improving power delivery in a memory, such as, a random access memory  
Embodiments of an apparatus and method to improve power delivery including a pre-charge circuit that may include a first voltage supply rail configured to provide a first voltage amount to perform...
8934313 Negative voltage generator and semiconductor memory device  
A negative voltage generator includes a variable-capacitance negative voltage generating unit, a switching unit and a positive voltage applying unit. The negative voltage generating unit includes a...
8929120 Diode segmentation in memory  
Memory devices, memory arrays, and methods of operation of memory arrays with segmentation. Segmentation elements can scale with the memory cells, and may be uni-directional or bi-directional...
8929153 Memory with multiple word line design  
Disclosed are various apparatuses and methods for a memory with a multiple read word line design. A memory may include a plurality of bit cells arranged in a row, a first read word line connected...
8929129 Semiconductor device  
A device, comprising: first and second signal lines; first and second transistors of first conductivity type coupled in series between first and second signal lines and coupled to each other at...
8917567 Semiconductor device having hierarchical bit line structure and control method thereof  
A semiconductor device includes a global bit line and a local bit line, and a switch coupled therebetween. Upon performing a precharge operation, a precharge voltage is supplied to the global bit...
8917557 Nonvolatile semiconductor memory device  
According to one embodiment, a nonvolatile semiconductor memory device comprises a semiconductor substrate, memory strings formed above the semiconductor substrate, and a control circuit configured...
8913452 Semiconductor device and semiconductor memory device  
A semiconductor device includes: a data transmission unit configured to transmit differential data between a first data line pair and a second data line pair; and first and second power supply...
8913439 Memory device and corresponding reading method  
An electrically erasable and programmable non-volatile memory device includes memory cells arranged in rows and columns, and each column of memory cells is associated with a respective local bit...
8913453 Semiconductor device and method of operating the same  
A semiconductor device including a memory block, which includes memory cells coupled to bit lines. The semiconductor device further includes a first sensing circuit coupled to an even bit line and...
8908461 Refresh circuit in semiconductor memory device  
A refresh circuit in a semiconductor memory device performs a multi-enable skew refresh operation during each periodic refresh operation. The refresh circuit includes a signal generation unit...
8908463 Nonvolatile semiconductor memory device and control method thereof  
A semiconductor memory device of this embodiment comprises: a plurality of memory chips each including a plurality of memory cells; and a controller that controls the plurality of memory chips. The...
8908456 Semiconductor memory device and operating method thereof  
An operating method of a semiconductor memory device includes precharging a channel region of a program-inhibited cell of first memory cells coupled to a first word line, selected from a first one...
8902646 Memory and method for operating the same  
A memory includes a first memory cell, a bit line corresponding to the first memory cell, at least one second memory cell adjacent to the first memory cell, and a page buffer configured to read...
8902659 Shared-bit-line bit line setup scheme  
Methods for operating a non-volatile storage system utilizing a shared-bit-line NAND architecture are described. A shared-bit-line NAND architecture includes one or more pairs of NAND strings,...
8897087 Memory device and operating method of memory device and memory system  
An operating method of a memory device includes entering a repair mode, receiving an active command and a fail address, and temporarily storing the received command and address, receiving a write...
8897082 Data transmission circuit and semiconductor memory device including the same  
The data transmission circuit includes: a plurality of local bit line pairs through which data is read simultaneously; a plurality of voltage change detection circuits provided for the plurality of...
8897054 ROM device with keepers  
A ROM memory circuit is disclosed having at least one electrical line, at least one keeper circuit electrically connected to the at least one electrical line, the keeper circuit including a first...
8891313 Memory device and read operation method thereof  
A read operation for a memory device. In response to an input address indicating to read data from a different page, a selected word line, first and second global bit lines and a selected first bit...
8891325 Circuit for driving word line  
A word line driving circuit includes, inter alia: a word line driving signal generator, a main word line enable signal controller, and a sub word line driver. The word line driving signal generator...
8891324 Memory device from which dummy edge memory block is removed  
A semiconductor memory device having an open bitline memory structure from which an edge dummy memory block is removed, the semiconductor memory device includes a memory block, an edge sense...
8885427 Precharge circuit and non-volatile memory device  
A precharge circuit includes a precharge unit configured to apply a voltage of a precharge voltage terminal to a data line during a precharge operation, and a sensing unit configured to disable the...
8885394 Semiconductor device with complementary global bit lines, operating method, and memory system  
A memory device includes sections arranged between a global bit line and a complementary global bit line, and having a section control unit disposed between first and second memory cell groups and...
8885433 Semiconductor device having fuse circuit  
A semiconductor device includes a pulse generation circuit configured to generate an enable pulse signal, which is activated in response to an active command signal and deactivated in response to a...
8887014 Managing errors in a DRAM by weak cell encoding  
This disclosure includes a method for preventing errors in a DRAM (dynamic random access memory) due to weak cells that includes determining the location of a weak cell in a DRAM row, receiving...
8879303 Pre-charge tracking of global read lines in high speed SRAM  
In embodiments of the invention, a memory circuit includes a static random access memory (SRAM), rows of M sense amplifiers, a global read precharge tracking control circuit controlling a precharge...
8879344 Phase change memory with flexible time-based cell decoding  
Methods and systems for time-based cell decoding for PCM memory. Generally, the higher the PCM element resistance, the longer it takes for a read output to change state. PCM memory output is...
8872686 Low glitch current digital-to-analog converter  
The present disclosure relates to a method and architecture to minimize a transient glitch within a current digital-to-analog converter (DAC) comprising an array of identical current unit cells....
8873314 Circuits and methods for providing data to and from arrays of memory cells  
A memory device uses a global input/output line or a pair of complementary global input/output lines to couple write data signals and read data signals to and from a memory array. The same...
8873321 Boosting supply voltage  
A data split between a first data line and a second data line is caused to develop. At least one of the following sets of steps is performed: 1) a first power supply line of a sense amplifier is...
8873301 Semiconductor memory device and method of operating the same  
A semiconductor memory device and a method of manufacturing the same are provided. The device includes a memory block and one or more peripheral circuits. The memory block includes a bit line, a...
8868829 Memory circuit system and method  
A method includes presenting multiple memory circuits to a system as a virtual memory circuit having at least one characteristic that is different from a corresponding characteristic of one of the...