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8913452 Semiconductor device and semiconductor memory device  
A semiconductor device includes: a data transmission unit configured to transmit differential data between a first data line pair and a second data line pair; and first and second power supply...
8913439 Memory device and corresponding reading method  
An electrically erasable and programmable non-volatile memory device includes memory cells arranged in rows and columns, and each column of memory cells is associated with a respective local bit...
8913453 Semiconductor device and method of operating the same  
A semiconductor device including a memory block, which includes memory cells coupled to bit lines. The semiconductor device further includes a first sensing circuit coupled to an even bit line and...
8908461 Refresh circuit in semiconductor memory device  
A refresh circuit in a semiconductor memory device performs a multi-enable skew refresh operation during each periodic refresh operation. The refresh circuit includes a signal generation unit...
8908463 Nonvolatile semiconductor memory device and control method thereof  
A semiconductor memory device of this embodiment comprises: a plurality of memory chips each including a plurality of memory cells; and a controller that controls the plurality of memory chips. The...
8908456 Semiconductor memory device and operating method thereof  
An operating method of a semiconductor memory device includes precharging a channel region of a program-inhibited cell of first memory cells coupled to a first word line, selected from a first one...
8902646 Memory and method for operating the same  
A memory includes a first memory cell, a bit line corresponding to the first memory cell, at least one second memory cell adjacent to the first memory cell, and a page buffer configured to read...
8902659 Shared-bit-line bit line setup scheme  
Methods for operating a non-volatile storage system utilizing a shared-bit-line NAND architecture are described. A shared-bit-line NAND architecture includes one or more pairs of NAND strings,...
8897087 Memory device and operating method of memory device and memory system  
An operating method of a memory device includes entering a repair mode, receiving an active command and a fail address, and temporarily storing the received command and address, receiving a write...
8897082 Data transmission circuit and semiconductor memory device including the same  
The data transmission circuit includes: a plurality of local bit line pairs through which data is read simultaneously; a plurality of voltage change detection circuits provided for the plurality of...
8897054 ROM device with keepers  
A ROM memory circuit is disclosed having at least one electrical line, at least one keeper circuit electrically connected to the at least one electrical line, the keeper circuit including a first...
8891313 Memory device and read operation method thereof  
A read operation for a memory device. In response to an input address indicating to read data from a different page, a selected word line, first and second global bit lines and a selected first bit...
8891325 Circuit for driving word line  
A word line driving circuit includes, inter alia: a word line driving signal generator, a main word line enable signal controller, and a sub word line driver. The word line driving signal generator...
8891324 Memory device from which dummy edge memory block is removed  
A semiconductor memory device having an open bitline memory structure from which an edge dummy memory block is removed, the semiconductor memory device includes a memory block, an edge sense...
8885427 Precharge circuit and non-volatile memory device  
A precharge circuit includes a precharge unit configured to apply a voltage of a precharge voltage terminal to a data line during a precharge operation, and a sensing unit configured to disable the...
8885394 Semiconductor device with complementary global bit lines, operating method, and memory system  
A memory device includes sections arranged between a global bit line and a complementary global bit line, and having a section control unit disposed between first and second memory cell groups and...
8885433 Semiconductor device having fuse circuit  
A semiconductor device includes a pulse generation circuit configured to generate an enable pulse signal, which is activated in response to an active command signal and deactivated in response to a...
8887014 Managing errors in a DRAM by weak cell encoding  
This disclosure includes a method for preventing errors in a DRAM (dynamic random access memory) due to weak cells that includes determining the location of a weak cell in a DRAM row, receiving...
8879303 Pre-charge tracking of global read lines in high speed SRAM  
In embodiments of the invention, a memory circuit includes a static random access memory (SRAM), rows of M sense amplifiers, a global read precharge tracking control circuit controlling a precharge...
8879344 Phase change memory with flexible time-based cell decoding  
Methods and systems for time-based cell decoding for PCM memory. Generally, the higher the PCM element resistance, the longer it takes for a read output to change state. PCM memory output is...
8872686 Low glitch current digital-to-analog converter  
The present disclosure relates to a method and architecture to minimize a transient glitch within a current digital-to-analog converter (DAC) comprising an array of identical current unit cells....
8873314 Circuits and methods for providing data to and from arrays of memory cells  
A memory device uses a global input/output line or a pair of complementary global input/output lines to couple write data signals and read data signals to and from a memory array. The same...
8873321 Boosting supply voltage  
A data split between a first data line and a second data line is caused to develop. At least one of the following sets of steps is performed: 1) a first power supply line of a sense amplifier is...
8873301 Semiconductor memory device and method of operating the same  
A semiconductor memory device and a method of manufacturing the same are provided. The device includes a memory block and one or more peripheral circuits. The memory block includes a bit line, a...
8868829 Memory circuit system and method  
A method includes presenting multiple memory circuits to a system as a virtual memory circuit having at least one characteristic that is different from a corresponding characteristic of one of the...
8867291 Semiconductor apparatus  
A semiconductor apparatus including an equalizing unit configured to equalize voltages of a bit line and a bit bar line in response to an equalization signal; a precharge circuit unit configured to...
8867292 Semiconductor device, method of retrieving data, and microcomputer  
A semiconductor device includes a data memory cell for storing data; a reference data memory cell for storing reference data to be compared with the data; an inverted data memory cell for storing...
8861285 Apparatuses and methods for line charge sharing  
Apparatuses and methods for charge sharing between signal lines are disclosed. An example apparatus may include first and second lines and a charge sharing circuit. The charge sharing circuit may...
8861264 Memory device, precharge controlling method thereof, and devices having the same  
A pre-charge controlling method and device are provided. The pre-charge controlling method includes pre-charging a first global bit line with a first pre-charge voltage by using at least a first...
8854909 Semiconductor memory device and method of testing the same  
A semiconductor memory device including an open bit line structure is disclosed. The semiconductor memory device including an open bit line structure includes a first mat, a second mat contiguous...
8848474 Capacitive coupled sense amplifier biased at maximum gain point  
A sense amplifier includes a first inverter including a first input node and a first output node, the first input node coupled to a first bitline through a first capacitor, the first output node...
8848426 Cross-point variable resistance nonvolatile memory device and reading method for cross-point variable resistance nonvolatile memory device  
A cross-point variable resistance nonvolatile memory device comprises: a memory cell array; a column decoder and pre-charge circuit which pre-charges a selected word line to a first voltage in a...
8842487 Power management domino SRAM bit line discharge circuit  
A domino static random access memory (SRAM) having one or more SRAM memory cells connected with a local bit line is disclosed. The SRAM may include a global bit line, a first precharge device...
8842483 Semiconductor device and method of operating the same  
A semiconductor device and a method of operating the same, the semiconductor device including a sense amplifier connected between a bit line and a complementary bit line; a first power supply...
8842480 Automated control of opening and closing of synchronous dynamic random access memory rows  
An apparatus including a protocol engine and a built-in self test (BIST) engine. The built-in self test (BIST) engine is coupled to the protocol engine. The built-in self test (BIST) engine may be...
8837244 Memory output circuit  
The invention provides a memory output circuit. The memory output circuit is capable of receiving bit line data and bit bar line data output by a memory cell array. In one embodiment, the memory...
8837234 Voltage control method to minimize a coupling noise between adjacent global bit lines during read-while operation and memory device using the same  
A memory device is provided, which includes a plurality of global bit lines, a discharge line, a switching circuit configured to connect the plurality of global bit lines to the discharge line in...
8824230 Method and apparatus of reducing leakage power in multiple port SRAM memory cell  
Systems and method for reducing leakage currents and power consumption in a memory array comprising memory cells, such as 8T SRAM cells. The memory array includes logic for dynamically placing a...
8824231 Reduced noise DRAM sensing  
A dynamic random access memory device is described. A first array has a first plurality of bitlines, each coupled to a column of memory cells. A second has a second plurality of bitlines, each...
8824229 Semiconductor memory apparatus having a pre-discharging function, semiconductor integrated circuit having the same, and method for driving the same  
A semiconductor memory apparatus includes a bit line coupled to a plurality of memory cells, a discharge controller configured to generate a bit line discharge signal to pre-discharge the bit line...
8824238 Memory device with bi-directional tracking of timing constraints  
A memory device includes a DRAM, a first bi-directional tracking circuit and a second bi-directional tracking circuit. The DRAM includes a cell, a word line and a bit line. The first bi-directional...
8824233 Systems, circuits, and methods for charge sharing  
Systems, circuits, and methods are disclosed for charge sharing. In one such example system, a first line is configured to be driven to a first voltage representative of data to be placed on the...
8824232 Semiconductor memory device and method of operating the same  
A semiconductor memory device may include a cell string configured to include memory cells, a page buffer coupled to the cell string through a bit line, and configured to include a latch for...
8824201 Semiconductor memory apparatus and data reading method thereof  
A semiconductor memory apparatus includes: a read current supply unit configured to supply a read current; a resistive memory cell configured to pass a current having a magnitude corresponding to a...
8817562 Devices and methods for controlling memory cell pre-charge operations  
A memory having a memory array having bit cells coupled to bit lines. The memory further includes a precharge circuit that precharges bit lines. The memory also includes a control circuit coupled...
8817554 Sense amplifiers, memories, and apparatuses and methods for sensing a data state of a memory cell  
Sense amplifiers, memories, and apparatuses and methods for sensing a data state of a memory cell are disclosed. An example apparatus includes a differential amplifier configured to amplify a...
8817567 Semiconductor memory device having low power mode and related method of operation  
A semiconductor memory device has a normal power mode and a low power mode. In the low power mode, a selection circuit assigns one data address to at least two memory cells in the semiconductor...
8811104 Semiconductor memory and system  
A semiconductor memory includes a real memory cell; a sense amplifier configured to amplify data read from the real memory cell in response to activation of a sense amplifier enable signal; a...
8811102 Multiple read port memory system with a single port memory cell  
An improved multi-port register file system and method of operating. The multi-port register file memory system comprises: n single memory bit cells each storing a data value and having a single...
8811111 Memory controller with reduced power consumption, memory device, and memory system  
A memory device comprising: at least one bank of memory cells that receives a first clock for clocking commands and a second clock for clocking data, wherein the second clock is activated based on...