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9070466 Mismatch error reduction method and system for STT MRAM  
The invention relates to methods and systems for reading a memory cell and in particular, an STT MRAM. In accordance with one aspect of the invention, a method for reading a memory cell includes...
9042148 Content addressable memory  
An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a...
9042187 Using a reference bit line in a memory  
Methods, memories and systems may include charging a sense node to a logic high voltage level, and supplying charge to a bit line and to a reference bit line for a precharge period that is based,...
9042162 SRAM cells suitable for Fin field-effect transistor (FinFET) process  
A static random access memory (SRAM) cell includes first and second n-channel transistors, first and second p-channel transistors, first and second enable transistors, and first and second pass...
9042198 Nonvolatile random access memory  
According to one embodiment, a memory includes a memory cell array with banks, each bank including rows, a first word lines provided in corresponding to the rows, an address latch circuit which...
9037930 Managing errors in a DRAM by weak cell encoding  
This disclosure includes a method for preventing errors in a DRAM (dynamic random access memory) due to weak cells that includes determining the location of a weak cell in a DRAM row, receiving...
9036403 Semiconductor memory devices  
The semiconductor memory device includes a cell capacitor having a first terminal electrically connected to a storage node and a second terminal electrically connected to an internal node, an...
9030900 Semiconductor device, semiconductor memory device and operation method thereof  
A semiconductor memory device includes a bit line sense amplification unit configured to sense/amplify data loaded on a bit line, and a driving control unit configured to supply a power line of...
9030901 Semiconductor memory device  
A semiconductor memory device includes a first memory block group including memory blocks coupled to first sub bit lines, a second memory block group including memory blocks coupled to second sub...
9030890 Semiconductor memory apparatus  
A semiconductor memory apparatus includes a sense amplifier driving control unit configured to be applied with first and second driving voltages, and generate first to third sense amplifier...
9030863 Read/write assist for memories  
An integrated circuit includes one or more bit cells, a word line coupled to the one or more bit cells, and a dummy word line arranged with the word line to have a capacitance therebetween. The...
9025403 Dynamic cascode-managed high-voltage word-line driver circuit  
A high-voltage word-line driver circuit for a memory device uses cascode devices to prevent any single transistor of the driver circuit from having the full power supply voltage from which the...
9025404 Semiconductor device with reduced leakage current and method for manufacture of the same  
A semiconductor device with reduced leakage current and a method of manufacturing these reduced leakage current semiconductor devices are disclosed. The reduced leakage current semiconductor...
9019787 Semiconductor device having hierarchical bit line structure  
A semiconductor device having hierarchical bit lines is disclosed, which comprises: a first global bit line; first and second local bit lines coupled in common to the first global bit line; first...
9019784 Data training device  
A data training device includes a training control block configured to activate driving signals for driving a bit line sense amplifier, with a word line deactivated, when a write training...
9019788 Techniques for accessing memory cells  
Techniques for accessing memory cells are disclosed. In one particular embodiment, the techniques may be realized as an apparatus providing voltage to a high impedance node of a memory cell. The...
9013938 Systems and methods for discharging load capacitance circuits  
Circuits, systems, and methods for discharging loads are provided. One circuit includes a node coupled to a voltage source, a capacitor, a source-follower device coupled between the node and the...
9013951 Word line drivers and semiconductor memory devices including the same  
Word line drivers including a selection signal generator and a word line drive unit are provided. The selection signal generator generates a selection signal which is enabled according to a...
9013939 Semiconductor memory device  
A semiconductor memory device includes a memory cell connected to a word line and a bit line, for storing and holding data, a word line driver circuit connected to the word line, a bit line...
9013940 Sense amplifier  
A sense amplifier comprises a cross coupled pair of inverters, a first transistor, a second transistor, and a capacitive device. The cross coupled pair of inverters includes a first end, a second...
9007857 SRAM global precharge, discharge, and sense  
An SRAM includes a global bit line, an SRAM cell, precharge logic, discharge logic, and sense logic. The SRAM cell stores a first logical value or a second logic value and is coupled to the global...
9007858 SRAM global precharge, discharge, and sense  
An SRAM includes a global bit line, an SRAM cell, precharge logic, discharge logic, and sense logic. The SRAM cell stores a first logical value or a second logic value and is coupled to the global...
9007817 Pre-charging bitlines in a static random access memory (SRAM) prior to data access for reducing leakage power, and related systems and methods  
Embodiments disclosed herein include methods and apparatuses for pre-charging bitlines in a static random access memory (SRAM) prior to data access for reducing leakage power. The memory access...
9007823 Semiconductor device  
A semiconductor device according to an embodiment includes: a first transistor including a gate connected to a first interconnection, a first source, and a first drain, one of the first source and...
9007859 Far end resistance tracking design with near end pre-charge control for faster recovery time  
A wordline tracking circuit and corresponding method are disclosed, and include a tracking wordline having an impedance characteristic associated therewith that models a row of memory cells in a...
9001562 Semiconductor memory device including a dummy block  
A semiconductor memory device includes a memory array including a plurality of element blocks; the plurality of element blocks including end-portion element blocks arranged at an end portion of...
9001604 Device and method for improving reading speed of memory  
A memory device includes a plurality of sense amplifiers coupled with an array of memory cells, a plurality of output data lines receiving outputs of corresponding sense amplifiers, and a...
9001591 Semiconductor device  
A semiconductor device including multiple subarrays arrayed in a matrix in the row and column directions, and respectively containing multiple memory cells, bit lines coupled to the memory cells,...
9003255 Automatic test-pattern generation for memory-shadow-logic testing  
An embodiment of a method for automated test pattern generation (ATPG), a system for ATPG, and a memory configured for ATPG. For example, an embodiment of a memory includes a first test memory...
8995211 Program condition dependent bit line charge rate  
Methods and devices for charging unselected bit lines are disclosed. The rate at which inhibited (or unselected) bit lines are charged may depend on a program condition. The program condition may...
8995175 Memory circuit with PMOS access transistors  
A memory circuit that includes a memory storage unit and access transistors coupled to the memory storage unit, where the access transistors include PMOS transistors, is described. In one...
8995214 Nonvolatile semiconductor memory  
According to one embodiment, a memory includes a temporary storage area which temporary stores data in a read/write operation to an array. The temporary storage area comprises a clamp FET...
8995208 Static random access memory devices having read and write assist circuits therein that improve read and write reliability  
Integrated circuit memory devices include a memory cell configured to receive a power supply signal and a write assist circuit. The write assist circuit is configured to improve write margins by...
8988920 Semiconductor memory device  
A semiconductor memory device according to an embodiment comprises: a plurality of memory cells arranged in a first direction and a second direction; local bit lines connected to group of the...
8988954 Memory device and method of performing a read operation within such a memory device  
A memory device is provided comprising an array of memory cells. During a read operation, voltage on a read bit line will transition towards a second voltage level if a data value stored in that...
8988962 Refresh circuit of a semiconductor memory device and refresh control method of the semiconductor memory device  
A refresh circuit and a semiconductor memory device including the refresh circuit are disclosed. The refresh circuit includes a mode register, a refresh controller and a multiplexer circuit. The...
8988958 Sense amplifier circuit and semiconductor device  
A single-ended sense amplifier circuit of the invention comprises first and second MOS transistors and first and second precharge circuits. The first MOS transistor drives the bit line to a...
8982652 Sense amplifier circuit and semiconductor device  
A single-ended sense amplifier circuit of the invention comprises first and second MOS transistors and first and second precharge circuits. The first MOS transistor drives the bit line to a...
8982659 Bitline floating during non-access mode for memory arrays  
Techniques are disclosed that allow for power conservation in integrated circuit memories, such as SRAM. The techniques can be embodied in circuitry that allows for floating of bitlines to...
8982609 Memory having read assist device and method of operating the same  
A memory includes a first bit line, a memory cell coupled to the first bit line, and a read assist device coupled to the first bit line. The read assist device is configured to pull a first...
8976601 Semiconductor memory apparatus  
A semiconductor memory apparatus includes a boundary circuit unit positioned between a low voltage page buffer and a high voltage page buffer and having circuits configured to electrically couple...
8976615 Semiconductor memory device capable of performing refresh operation without auto refresh command  
A semiconductor memory device includes an internal address generating circuit; an internal command generating circuit; and a memory cell array including one or more memory bank groups. The...
8976612 Sense amplifier circuit and semiconductor device  
A single-ended sense amplifier circuit of the invention comprises first and second MOS transistors and first and second precharge circuits. The first MOS transistor drives the bit line to a...
8976610 Memory device with timing overlap mode  
In some examples, a memory device is configured to receive a precharge command and an activate command. The memory device performs a first series of events related to the precharge command in...
8976600 Word line driver circuit for selecting and deselecting word lines  
A memory circuit includes word lines coupled to a memory array, including a first set of one or more word lines deselected in an erase operation, and a second set of one or more word lines...
8971131 Data circuit  
A circuit includes a first plurality of memory cells coupled with a first data line and a first data transfer circuit coupled with the first data line and a second data line. In a first operation...
8971141 Compact high speed sense amplifier for non-volatile memory and hybrid lockout  
A compact and versatile high speed sense amplifier suitable for use in non-volatile memory circuits is presented. The sense amp circuit uses one power supply level for the bit line driving path...
8971140 Semiconductor device and data processing system comprising semiconductor device  
A semiconductor device comprises a sense amplifier circuit amplifying a signal transmitted through the bit line, first/second data lines transmitting the signal amplified by the sense amplifier...
8964445 Ferroelectric random access memory with isolated power supply during write and write-back cycles  
In an embodiment of the invention, a method is provided for isolating a ferroelectric memory from a power supply during a write-back cycle or a write cycle of the ferroelectric memory. After it is...
8964496 Apparatuses and methods for performing compare operations using sensing circuitry  
The present disclosure includes apparatuses and methods related to performing compare and/or report operations using sensing circuitry. An example method can include charging an input/output (IO)...