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RE45036 Semiconductor memory device  
A semiconductor memory device includes a first first-type well including a first cell array for storing a data to apply the data to one of a first bit line and a first bit line bar, and a first...
8787102 Memory device and signal processing circuit  
A memory device which can keep a stored logic state even when the power is off is provided. A signal processing circuit including the memory device, which achieves low power consumption by stopping...
8787059 Cascaded content addressable memory array having multiple row segment activation  
A content addressable memory (CAM) device has an array including a plurality of CAM rows that are partitioned into row segments, wherein a respective row includes a first row segment including a...
8780658 Leakage reduction in memory devices  
A memory device includes a core array that includes memory cells. The memory device also includes a headswitch coupled to the core array and a positive supply voltage. The headswitch reduces...
8773924 Read assist scheme for reducing read access time in a memory  
A read circuit includes a precharge circuit, coupled with at least a subset of bit lines and a sense circuit in a memory, and a transmission gate. The precharge circuit receives a first control...
8773933 Techniques for accessing memory cells  
Techniques for accessing memory cells are disclosed. In one particular embodiment, the techniques may be realized as an apparatus providing voltage to a high impedance node of a memory cell. The...
8767503 Clock transfer circuit and semiconductor device including the same  
A clock transfer circuit includes a clock transfer unit configured to receive an external clock and transfer the received external clock as one or more internal clocks and a clock control unit...
8767494 Far end resistance tracking design with near end pre-charge control for faster recovery time  
A wordline tracking circuit and corresponding method are disclosed, and include a tracking wordline having an impedance characteristic associated therewith that models a row of memory cells in a...
RE44978 Method of verifying programming of a nonvolatile memory device  
A first verify voltage is applied to a word line of a selected memory cell, after a bit line is precharged, to program-verify the memory cell in a nonvolatile memory device. A first read evaluation...
8767492 Methods and systems to read register files with un-clocked read wordlines and clocked bitlines, and to pre-charge a biteline to a configurable voltage  
A method and system to improve the operations of a memory device by reducing its bit line leakage, power consumption, and read access time. The memory device has a static read word line for each of...
8767493 SRAM differential voltage sensing apparatus  
An SRAM differential voltage sensing apparatus is coupled to a memory circuit. The memory circuit comprises a memory bank, a plurality of bit lines, a plurality of data lines coupled to the...
8760951 Method of reading data in a non-volatile memory device  
A method of reading data in a non-volatile memory device compensates for a change in a reading/verifying result in accordance with a change of temperature. The method includes sensing a temperature...
8760943 Semiconductor apparatus  
A semiconductor apparatus according to an aspect of the present invention includes first and second bus-interface circuits, a first memory core connected to the first bus-interface circuit through...
8755217 Semiconductor memory device  
A semiconductor memory device includes a memory cell connected to a read bit line and a pair of write bit lines, and a data amplifier connected to the read bit line. A precharge potential resetting...
8755234 Temperature based compensation during verify operations for non-volatile storage  
A non-volatile storage system that performs programming and reading processes. The programming process includes coarse/fine programming and verify operations. Programming is verified by testing for...
8750054 Data input/output circuit and semiconductor memory device  
A data input/output circuit includes: an amplification unit configured to generate a data signal by amplifying data of a first input/output line coupled to a bank during a read operation, and...
8750063 Sense amplifier control circuit and semiconductor memory device including the same  
A sense amplifier control circuit according to the present invention is disposed in a bit line sense amplifier (BLSA) array region including a plurality of BLSAs and is configured to supply a...
8743639 Semiconductor memory device  
A semiconductor memory device includes a switching unit coupled between a local sense amplifier and a bit line sense amplifier and configured to be turned on in response to a switching signal which...
8743630 Current sense amplifier with replica bias scheme  
Some embodiments of the present disclosure relate to a sense amplifier architecture that facilitates fast and accurate read operations. The sense amplifier architecture includes a folded cascode...
8743590 Memory device and semiconductor device using the same  
A memory device whose speed at the time of operation such as writing or reading is high and whose number of semiconductor elements per memory cell is small is provided. The memory device includes a...
8743627 Memory device and voltage interpreting method for read bit line  
A memory device comprises a memory cell array, a first and a second pre-charging switch circuits, a selecting circuit, an auxiliary memory cell array, a dynamic voltage controller and a sense...
8737151 Low read current architecture for memory  
A low read current architecture for memory. Bit lines of a cross point memory array are allowed to be charged by a selected word line until a minimum voltage differential between a memory state and...
8737162 Clock-forwarding low-power signaling system  
In a low-power signaling system, an integrated circuit device includes an open loop-clock distribution circuit and a transmit circuit that cooperate to enable high-speed transmission of...
8737152 Semiconductor memory device and method of testing the same  
A semiconductor memory device including an open bit line structure is disclosed. The semiconductor memory device including an open bit line structure includes a first mat, a second mat contiguous...
8737158 Semiconductor device and method of controlling the same  
A device includes a command decoder that is configured to output, in a normal operation mode, a precharge signal in response to a first type transition edge of a synchronous signal, and an active...
8730712 SRAM including write assist circuit and method of operating same  
A static random access memory (SRAM) is described and includes; a bit cell connected with a word line, connected between a bit line and a complementary bit line, and receiving an internal voltage...
8730748 Semiconductor memory apparatus equipped with an error control circuit for preventing coupling noise  
A semiconductor memory apparatus includes a plurality of memory banks, wherein each memory bank includes a bank control unit configured to reduce a voltage level of a first node to a ground voltage...
8724390 Architecture for a 3D memory array  
Techniques are described herein for compensating for threshold voltage variations among memory cells in an array by applying different bias conditions to selected bit lines. Techniques are also...
8724412 Voltage supply circuit, semiconductor memory device, and operating method thereof  
A voltage supply circuit includes a high voltage generator configured to generate an operating voltage, a global word line switch configured to transfer the operating voltage to global word lines,...
8723878 Display device integrated circuit (DDI) with adaptive memory control and adaptive memory control method for DDI  
A graphics memory device includes a memory array configured to store data for a display device comprising b*y rows by a*x columns of pixels, where b>a. The memory array is arranged in a*y rows by...
8724411 Memory devices and memory systems including discharge lines  
A non-volatile memory device can include a word line that is operatively coupled to a non-volatile memory cell. A local bit line can be operatively coupled to the non-volatile memory cell. A...
8724359 Methods and circuits for limiting bit line leakage current in a content addressable memory (CAM) device  
A content addressable memory (CAM) device can include a number of bit lines. One or more of the bit lines can be connected to storage circuits of CAM cells in a corresponding column. Each CAM cell...
8717825 Memory device and corresponding reading method  
An electrically erasable and programmable non-volatile memory device includes memory cells arranged in rows and columns, and each column of memory cells is associated with a respective local bit...
8711642 Interleaving charge pumps for programmable memories  
Systems and methods, including computer software for performing operations enable interleaving of charging operations in a charging pump. A first charge pump is charged to a predetermined level,...
8711635 Nonvolatile semiconductor memory device  
A nonvolatile semiconductor memory device includes a memory cell which stores data and which is capable of being rewritten electrically, a bit line which is connected electrically to one end of a...
8705303 Semiconductor device and control method of the same  
The present invention provides a semiconductor memory and a control method therefor, the semiconductor device including a first current-voltage conversion circuit connected to a core cell provided...
8705302 Semiconductor memory devices having self-refresh capability  
A semiconductor memory device includes at least one memory bank including a plurality of memory cells and a self-refresh controller configured to generate a refresh address and to output a row...
8705300 Memory array circuitry with stability enhancement features  
Integrated circuits such as programmable logic device integrated circuits are provided that have memory arrays with memory cells arranged in rows and columns. Address lines may be associated with...
8699288 Pre-charge voltage generation and power saving modes  
A system includes a voltage generator to produce a pre-charge voltage signal for pre-charging one or more signals in a memory circuit. The one or more signals can be data bus lines used to access...
8699291 Memory circuitry with dynamic power control  
Circuits and techniques for operating a memory circuit are disclosed. A disclosed circuit includes a memory circuit and a sleep circuit with an output terminal coupled to the memory circuit. The...
8693279 Synchronous global controller for enhanced pipelining  
A system includes a memory block and a controller. The controller is adapted to skew a pre-charge signal for a bit line of the memory block. The controller can skew the pre-charge signal during a...
8693260 Memory array with two-phase bit line precharge  
An integrated circuit includes an array of memory cells with a plurality of columns and rows. A plurality of data lines is coupled to the columns in the array and a plurality of word lines is...
8687448 Semiconductor memory device and sense amplifier  
A semiconductor memory device comprises a memory cell; a first bit line and a second bit line connected to the memory cell; and a sense amplifier operative to amplify the voltage between the first...
8687447 Semiconductor memory apparatus and test method using the same  
A semiconductor memory apparatus includes: a precharge voltage control unit configured to selectively output a bit line precharge voltage or a core voltage as a control voltage in response to a...
8687459 Synchronous command-based write recovery time auto-precharge control  
Methods of operating a memory device and memory devices are provided. For example, a method of operating a memory array is provided that includes a synchronous path and an asynchronous path. A...
8681576 Pre-charge and equalization devices  
A circuit comprises a set of pre-charge and equalization devices, a control signal line, and a word line. The set of pre-charge and equalization devices is configured to pre-charge and equalize a...
8681577 Semiconductor memory integrated device having a precharge circuit with thin-film transistors gated by a voltage higher than a power supply voltage  
Provided is a semiconductor integrated device including a semiconductor memory circuit and a peripheral circuit of the semiconductor memory circuit. The peripheral circuit includes a first...
8675421 Semiconductor memory device  
A semiconductor memory device includes a first page buffer group including a plurality of page buffers coupled to memory cells of a first memory array through bit lines, a second page buffer group,...
8675439 Bit line voltage bias for low power memory design  
In a digital memory with an array of bit cells coupled to word lines and bit lines, each bit cell having cross coupled inverters isolated from bit lines by passing gate transistors until addressed,...
8675427 Implementing RC and coupling delay correction for SRAM  
A method and circuit for implementing delay correction in static random access memory (SRAM), and a design structure on which the subject circuit resides are provided. The SRAM circuit includes a...