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9013938 Systems and methods for discharging load capacitance circuits  
Circuits, systems, and methods for discharging loads are provided. One circuit includes a node coupled to a voltage source, a capacitor, a source-follower device coupled between the node and the...
9013951 Word line drivers and semiconductor memory devices including the same  
Word line drivers including a selection signal generator and a word line drive unit are provided. The selection signal generator generates a selection signal which is enabled according to a...
9013939 Semiconductor memory device  
A semiconductor memory device includes a memory cell connected to a word line and a bit line, for storing and holding data, a word line driver circuit connected to the word line, a bit line...
9013940 Sense amplifier  
A sense amplifier comprises a cross coupled pair of inverters, a first transistor, a second transistor, and a capacitive device. The cross coupled pair of inverters includes a first end, a second...
9007857 SRAM global precharge, discharge, and sense  
An SRAM includes a global bit line, an SRAM cell, precharge logic, discharge logic, and sense logic. The SRAM cell stores a first logical value or a second logic value and is coupled to the global...
9007858 SRAM global precharge, discharge, and sense  
An SRAM includes a global bit line, an SRAM cell, precharge logic, discharge logic, and sense logic. The SRAM cell stores a first logical value or a second logic value and is coupled to the global...
9007817 Pre-charging bitlines in a static random access memory (SRAM) prior to data access for reducing leakage power, and related systems and methods  
Embodiments disclosed herein include methods and apparatuses for pre-charging bitlines in a static random access memory (SRAM) prior to data access for reducing leakage power. The memory access...
9007823 Semiconductor device  
A semiconductor device according to an embodiment includes: a first transistor including a gate connected to a first interconnection, a first source, and a first drain, one of the first source and...
9007859 Far end resistance tracking design with near end pre-charge control for faster recovery time  
A wordline tracking circuit and corresponding method are disclosed, and include a tracking wordline having an impedance characteristic associated therewith that models a row of memory cells in a...
9001562 Semiconductor memory device including a dummy block  
A semiconductor memory device includes a memory array including a plurality of element blocks; the plurality of element blocks including end-portion element blocks arranged at an end portion of the...
9001604 Device and method for improving reading speed of memory  
A memory device includes a plurality of sense amplifiers coupled with an array of memory cells, a plurality of output data lines receiving outputs of corresponding sense amplifiers, and a plurality...
9001591 Semiconductor device  
A semiconductor device including multiple subarrays arrayed in a matrix in the row and column directions, and respectively containing multiple memory cells, bit lines coupled to the memory cells,...
9003255 Automatic test-pattern generation for memory-shadow-logic testing  
An embodiment of a method for automated test pattern generation (ATPG), a system for ATPG, and a memory configured for ATPG. For example, an embodiment of a memory includes a first test memory...
8995211 Program condition dependent bit line charge rate  
Methods and devices for charging unselected bit lines are disclosed. The rate at which inhibited (or unselected) bit lines are charged may depend on a program condition. The program condition may...
8995175 Memory circuit with PMOS access transistors  
A memory circuit that includes a memory storage unit and access transistors coupled to the memory storage unit, where the access transistors include PMOS transistors, is described. In one...
8995214 Nonvolatile semiconductor memory  
According to one embodiment, a memory includes a temporary storage area which temporary stores data in a read/write operation to an array. The temporary storage area comprises a clamp FET connected...
8995208 Static random access memory devices having read and write assist circuits therein that improve read and write reliability  
Integrated circuit memory devices include a memory cell configured to receive a power supply signal and a write assist circuit. The write assist circuit is configured to improve write margins by...
8988920 Semiconductor memory device  
A semiconductor memory device according to an embodiment comprises: a plurality of memory cells arranged in a first direction and a second direction; local bit lines connected to group of the...
8988954 Memory device and method of performing a read operation within such a memory device  
A memory device is provided comprising an array of memory cells. During a read operation, voltage on a read bit line will transition towards a second voltage level if a data value stored in that...
8988962 Refresh circuit of a semiconductor memory device and refresh control method of the semiconductor memory device  
A refresh circuit and a semiconductor memory device including the refresh circuit are disclosed. The refresh circuit includes a mode register, a refresh controller and a multiplexer circuit. The...
8988958 Sense amplifier circuit and semiconductor device  
A single-ended sense amplifier circuit of the invention comprises first and second MOS transistors and first and second precharge circuits. The first MOS transistor drives the bit line to a...
8982652 Sense amplifier circuit and semiconductor device  
A single-ended sense amplifier circuit of the invention comprises first and second MOS transistors and first and second precharge circuits. The first MOS transistor drives the bit line to a...
8982659 Bitline floating during non-access mode for memory arrays  
Techniques are disclosed that allow for power conservation in integrated circuit memories, such as SRAM. The techniques can be embodied in circuitry that allows for floating of bitlines to...
8982609 Memory having read assist device and method of operating the same  
A memory includes a first bit line, a memory cell coupled to the first bit line, and a read assist device coupled to the first bit line. The read assist device is configured to pull a first voltage...
8976601 Semiconductor memory apparatus  
A semiconductor memory apparatus includes a boundary circuit unit positioned between a low voltage page buffer and a high voltage page buffer and having circuits configured to electrically couple...
8976615 Semiconductor memory device capable of performing refresh operation without auto refresh command  
A semiconductor memory device includes an internal address generating circuit; an internal command generating circuit; and a memory cell array including one or more memory bank groups. The...
8976612 Sense amplifier circuit and semiconductor device  
A single-ended sense amplifier circuit of the invention comprises first and second MOS transistors and first and second precharge circuits. The first MOS transistor drives the bit line to a...
8976610 Memory device with timing overlap mode  
In some examples, a memory device is configured to receive a precharge command and an activate command. The memory device performs a first series of events related to the precharge command in...
8976600 Word line driver circuit for selecting and deselecting word lines  
A memory circuit includes word lines coupled to a memory array, including a first set of one or more word lines deselected in an erase operation, and a second set of one or more word lines selected...
8971131 Data circuit  
A circuit includes a first plurality of memory cells coupled with a first data line and a first data transfer circuit coupled with the first data line and a second data line. In a first operation...
8971141 Compact high speed sense amplifier for non-volatile memory and hybrid lockout  
A compact and versatile high speed sense amplifier suitable for use in non-volatile memory circuits is presented. The sense amp circuit uses one power supply level for the bit line driving path and...
8971140 Semiconductor device and data processing system comprising semiconductor device  
A semiconductor device comprises a sense amplifier circuit amplifying a signal transmitted through the bit line, first/second data lines transmitting the signal amplified by the sense amplifier...
8964445 Ferroelectric random access memory with isolated power supply during write and write-back cycles  
In an embodiment of the invention, a method is provided for isolating a ferroelectric memory from a power supply during a write-back cycle or a write cycle of the ferroelectric memory. After it is...
8964496 Apparatuses and methods for performing compare operations using sensing circuitry  
The present disclosure includes apparatuses and methods related to performing compare and/or report operations using sensing circuitry. An example method can include charging an input/output (IO)...
8964449 Semiconductor memory device  
A semiconductor memory device selects one of a plurality of memory cells as a dummy memory cell. The dummy memory cell is connected to a bit line that is complementary to a bit line connected to a...
8964439 Semiconductor device having hierarchical bit line structure  
A semiconductor device comprises first and second global bit lines, a sense amplifier amplifying a voltage difference of the first and second global bit lines, first and second local bit lines...
8958254 High performance two-port SRAM architecture using 8T high performance single port bit cell  
An 8T memory bit cell receives a clock signal and read and write address signals. A read address latch/clock circuit receives the clock signal and the read address signals and initiates a read...
8953401 Memory device and method for driving memory array thereof  
A memory array includes a plurality of columns of memory cells and each column of memory cells of the memory array is coupled to a local voltage source, a bit line, and a bit line bar. Provide a...
8953399 Differential sense amplifier without dedicated pass-gate transistors  
A differential sense amplifier for sensing data stored in a plurality of memory cells of a memory cell array, including a first CMOS inverter having an output connected to a first bit line and an...
8953400 Data control circuit  
The data control circuit includes an input/output line and a driver. The input/output line precharging circuit precharges a global input/output line to a predetermined voltage when either a reading...
8947967 Shared integrated sleep mode regulator for SRAM memory  
Embodiments are described for a method for regulating sleep mode of a plurality of sub-banks in an SRAM array by isolating all of the sub-banks from a regulator upon access to at least one sub-bank...
8947968 Memory having power saving mode  
A memory has a normal mode and a power saving mode. The memory has bitline precharge circuitry which during the normal mode selectively couples a pair of bitlines to a precharge node to charge the...
8947963 Variable pre-charge levels for improved cell stability  
Embodiments of a memory device are disclosed that may allow for multiple pre-charge voltages. The memory device may include a plurality of data lines, and a plurality of pre-charge circuits. Each...
8947960 Semiconductor storage with a floating detection circuitry and floating detection method thereof  
A storage medium including a plurality of memory cells, a plurality of transmission lines, a driving module and a floating detection module is disclosed. The memory cells store data. The...
8942052 Complementary metal-oxide-semiconductor (CMOS) min/max voltage circuit for switching between multiple voltages  
A voltage selection mechanism is provided for switching between multiple voltages without causing a direct current (DC) that may further stress storage elements due to excessive power consumption...
8942021 Semiconductor device  
A semiconductor device includes: an I/O circuit configured to input/output a data signal; a plurality of internal circuits configured to transmit and receive the data signal to/from the I/O...
8937841 Driver for semiconductor memory and method thereof  
A driver for a semiconductor memory includes: a selection controller configured to output a target charge current select signal and a bucket charge current select signal in response to an inputted...
8934314 Apparatus and method for improving power delivery in a memory, such as, a random access memory  
Embodiments of an apparatus and method to improve power delivery including a pre-charge circuit that may include a first voltage supply rail configured to provide a first voltage amount to perform...
8934313 Negative voltage generator and semiconductor memory device  
A negative voltage generator includes a variable-capacitance negative voltage generating unit, a switching unit and a positive voltage applying unit. The negative voltage generating unit includes a...
8929120 Diode segmentation in memory  
Memory devices, memory arrays, and methods of operation of memory arrays with segmentation. Segmentation elements can scale with the memory cells, and may be uni-directional or bi-directional...