Patents in Class 365/203

Matches 1 - 50 out of 2874

Match	Document	Document Title
1	RE44218	Semiconductor memory device for controlling write recovery time A semiconductor memory device includes a CAS latency mode detecting means for outputting a CAS latency control signal in response to a CAS latency mode; and an auto-precharge control means for...
2	8441877	Semiconductor memory devices including burn-in test circuits A semiconductor memory device includes a memory cell array including a first memory cell coupled to a first bit line and a word line, and a second memory cell coupled to a second bit line and the...
3	8441874	Memory device with robust write assist A memory circuit includes a memory cell configured to be re-writable. A write enable circuit is configured to enable writing a signal via a pair of bit lines to the memory cell depending on a write...
4	8437191	Flash memory device and operating method thereof A flash memory device includes a memory cell string including a plurality of memory cells serially coupled to one another between a bit line and a source line, a page buffer configured to perform a...
5	8432764	Boost cell supply write assist A method of increasing a drain to source voltage measured at an access pass-gate to a SRAM circuit in a SRAM memory array, including increasing a low voltage from a low voltage source powering said...
6	8432761	Data bus control scheme for and image sensor and image sensor including the same A memory system including a plurality of memory cells configured to receive digital signals includes an address decoder, a data bus, and a sense amplifier configured to receive data output from...
7	8432386	Switch device for source driver of liquid crystal display and operating method thereof A switch device for source drivers of liquid crystal displays includes a first switch module; a first switch; a second switch; a second switch module; a third switch module; a fourth switch module;...
8	8422309	Voltage generation circuit and nonvolatile memory device using the same A voltage generation circuit comprises a voltage generation control unit configured to output one of a first voltage level determination signal having a fixed data value and a second voltage level...
9	8422325	Precharge control circuit and integrated circuit including the same A precharge control circuit includes a precharge voltage supply unit for generating a precharge voltage according to a voltage level of a precharge control signal, a voltage generator for...
10	8422308	Block decoder of flash memory device A block decoder of a flash memory device includes a discharge control unit configured to output a discharge signal in response to a program precharge signal and one or more of a number of address...
11	8416632	Bitline precharge voltage generator, semiconductor memory device comprising same, and method of trimming bitline precharge voltage A bitline precharge voltage generator comprises a leakage trimming unit and a bitline precharge voltage providing unit. The leakage trimming unit applies a leakage current to an output node to...
12	8416628	Local sensing in a memory device Methods for sensing, memory devices, and memory systems are disclosed. In one such memory device, a local sense circuit provides sensing of an upper group of memory cells while a global sense...
13	8406073	Hierarchical DRAM sensing A hierarchical DRAM sensing apparatus and method which employs local bit line pairs and global bit lines. A word line selects the cells in a cluster of sense amplifiers, each of the amplifiers...
14	8400855	Semiconductor device A semiconductor device includes a data transmission line and a data transmission line precharge circuit. The data transmission line precharge circuit sets a precharge potential of the data...
15	8400856	Memory device with data prediction based access time acceleration A memory device includes a memory array including a plurality of memory cells, sensing circuitry coupled to at least a given bitline associated with a particular column of the memory cells of the...
16	8395953	Bit-line sense amplifier, semiconductor memory device having the same, and method of testing bit-line micro-bridge defect The bit-line sense amplifier includes a driving-voltage control circuit and an amplifier. The driving-voltage control circuit generates a first test driving voltage having a voltage level of a...
17	8395949	Semiconductor integrated circuit and method for controlling the same A semiconductor integrated circuit includes: a current difference sense type of a sense amplifier including: an input line connected to memory cells as a target to be read, a reference line...
18	8391092	Circuit and method for eliminating bit line leakage current in random access memory devices A method for eliminating bit line leakage current of a memory cell in random access memory devices comprises the steps of: periodically activating a pre-charge equalization circuit, which provides...
19	8385146	Memory throughput increase via fine granularity of precharge management Methods and apparatus to improve throughput in memory devices are described. In one embodiment, memory throughput is increased via fine granularity of precharge management. In an embodiment, three...
20	8379469	Integrated circuit memory operation apparatus and methods Some embodiments include apparatus and methods having a memory cell included in a device, a control line configured to receive a control signal to access the memory cell, and a first line...
21	8379467	Structure and methods for measuring margins in an SRAM bit Integrated circuit for performing test operation of static RAM bit and for measuring the read margin, write margin, and stability margin of SRAM bits with operational circuitry that includes...
22	8379480	Non-volatile memory device and method of manufacturing the same A multi-layered non-volatile memory device and a method of manufacturing the same. The non-volatile memory device may include a plurality of first semiconductor layers having a stack structure. A...
23	8375241	Method and system to improve the operations of a registered memory module A method and system to improve the operations of a registered memory module. In one embodiment of the invention, the registered memory module allows asynchronous read and write operations when a...
24	8369177	Techniques for reading from and/or writing to a semiconductor memory device Techniques for reading from and/or writing to a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus including a first...
25	8369156	Fast random access to non-volatile storage Techniques are disclosed herein for efficiently operating memory arrays of non-volatile storage devices. In one embodiment, when reading data from an MLC block, reading is sped up by not...
26	8369168	Devices and system providing reduced quantity of interconnections Methods, devices and systems for reducing the quantity of external interconnections of a memory device are disclosed. Implementation of one such method, device and system includes inputting over an...
27	8363448	Semiconductor memory device According to one embodiment, a semiconductor memory device includes a memory cell, a power supply circuit, an interconnection and a discharging circuit. The memory cell includes a variable...
28	8363489	Semiconductor device having bit line equalization using low voltage and a method thereof A semiconductor memory device that can minimize the area of a circuit for generating a BLEQ signal by using one power source voltage terminal floated for the generation of a BLEQ signal. The...
29	8363497	Data control circuit The data control circuit includes an input/output line and a driver. The input/output line precharging circuit precharges a global input/output line to a predetermined voltage when either a reading...
30	8363498	Non-volatile memory device A non-volatile memory device includes a plurality of mats, each of which includes a unit cell in an intersection area between each of a plurality of word lines and each of a plurality of bit lines...
31	8363453	Static random access memory (SRAM) write assist circuit with leakage suppression and level control A static random access memory (SRAM) write assist circuit with leakage suppression and level control is described. In one embodiment, the SRAM write assist circuit increases the amount of boost...
32	8363490	Circuits, systems and methods for driving high and low voltages on bit lines in non-volatile memory An integrated circuit bit line driver system includes a plurality of bit line drivers coupled to respective bit lines of an array of non-volatile memory cells. Each of the bit line drivers includes...
33	8358524	Methods and circuits for limiting bit line leakage current in a content addressable memory (CAM) device A content addressable memory (CAM) device can include a number of bit line. One or more of the bit lines can be connected to storage circuits of CAM cells in a corresponding column. Each CAM cell...
34	8358550	Memory Program Discharge Circuit of bit lines with multiple discharge paths A memory integrated circuit has an array of nonvolatile memory cells, bit lines accessing the array of nonvolatile memory cells, and bit line discharge circuitry. The bit lines have multiple...
35	8358551	Reducing peak currents required for precharging data lines in memory devices A semiconductor memory storage device is disclosed. The semiconductor memory storage devices comprises: a plurality of data storage cells arranged in an array. The array comprises a plurality of...
36	8354863	Control signal generation circuit and sense amplifier circuit using the same A control signal generation circuit includes a voltage detection unit which detects a level of an external voltage and generates first and second detection signals and a control signal control unit...
37	8355288	Semiconductor memory device with temperature sensing device capable of minimizing power consumption in refresh A semiconductor memory device capable of measuring a temperature without the influence of noise includes a temperature sensing device for sensing a current temperature in response to a control...
38	8351278	Jam latch for latching memory array output data A jam latch device for a data node includes a feed forward inverter having an input coupled to the data node; a feedback inverter having an input connected to an output of the feed forward inverter...
39	8351287	Bitline floating circuit for memory power reduction Techniques are provided which may be used to reduce power consumed by memory circuits. In one example, a memory circuit includes a static random access memory (SRAM) cell. A pair of bitlines are...
40	8345469	Static random access memory (SRAM) having bit cells accessible by separate read and write paths A method is for reading a first bit cell of a static random access memory in which the static random access memory has a first plurality of bit cells including the first bit cell. Each bit cell of...
41	8345497	Internal bypassing of memory array devices An output control circuit for a memory array includes a latched output node precharged to a first logic state prior to both a read and write operation; first logic that couples memory cell data...
42	8339835	Nonvolatile memory element and semiconductor memory device including nonvolatile memory element A nonvolatile memory element includes a current controlling element having a non-linear current-voltage characteristic, a resistance variable element which changes reversibly between a...
43	8339884	Low power and high speed sense amplifier A sense amplifier circuit includes a precharge circuit configured to precharge a bit line coupled to a sensing node in response to a precharge control signal and a sense output circuit. The sense...
44	8339893	Dual beta ratio SRAM A static random access memory (SRAM) cell includes a first read port, the first read port having a first beta ratio; and a write port, the write port having a second beta ratio that is...
45	8339883	Semiconductor memory device A semiconductor memory device includes a bitline sensing amp detecting and amplifying data of a pair of bitlines from a memory cell, a column selecting unit transmitting the data of the pair of...
46	8339882	Dual bit line precharge architecture and method for low power dynamic random access memory (DRAM) integrated circuit devices and devices incorporating embedded DRAM A dual bit line precharge architecture and method for low power DRAM which provides the low operating voltage of a non-half supply voltage (VCC/2) precharge with the low memory array current...
47	8335120	Semiconductor memory circuit and control method for reading data A semiconductor memory device includes a first memory circuits connecting to a first bit line, a second bit line and a word line, a first pre-charge control circuit connecting to a first pre-charge...
48	8331180	Active bit line droop for read assist A static random access memory (SRAM) includes an SRAM cell to store a bit of data. A word line accesses the SRAM cell, which, responsively, during a read, drives either a bit line true (BLT) or a...
49	8331165	Semiconductor device A semiconductor device includes a plurality of first output terminals 1-13 and a plurality of first output circuits 203,204 provided corresponding to each of the plurality of first output terminals...
50	8330496	Semiconductor integrated circuit device An object of the present invention is to provide a technique of reducing the leakage current of a drive circuit for driving a circuit that must retain a potential (or information) when in its...

Matches 1 - 50 out of 2874

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