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7619939 Semiconductor storage apparatus  
A cell array selection circuit, a cell array bit line precharge circuit, and a sense amplifier bit line precharge circuit are provided in a semiconductor storage apparatus. In a standby state of...
7619928 Semiconductor memory device including floating body memory cells and method of operating the same  
A semiconductor memory device includes first and second memory cells having floating bodies, each of which includes a gate connected to a word line and an electrode connected to a common source...
7616511 Input/output line sense amplifier and semiconductor memory device using the same  
An input/output (I/O) line sense amplifier includes a buffer unit, a sense amplifier, and a precharge unit. The buffer unit is driven by a first level voltage to buffer a strobe signal, and the...
7616510 Dynamic semiconductor storage device and method for operating same  
The object of the present invention is to provide a DRAM, in which the operation speed for a sense amplifier can be increased. Bit line precharging circuits PCt and PCb are arranged to precharge...
7616471 Ferroelectric memory device  
A ferroelectric memory array includes a plurality of bit lines; a plurality of memory cells connected to the bit lines and storing predetermined data; and a plurality of sense amplifiers provided...
7613057 Circuit and method for a sense amplifier  
A circuit and method for providing a sense amplifier for a DRAM memory with reduced distortion in a control signal, the sense amplifier particularly useful for embedding DRAM memory with other...
7609571 Semiconductor memory device having a control unit receiving a sensing block selection address signal and related method  
Embodiments of the invention include a semiconductor memory device and a method for operating the semiconductor memory device. The invention includes a semiconductor memory device comprising a...
7606109 Word line driving circuit and semiconductor device using the same  
A word line driving circuit and a semiconductor device using the same are disclosed. The word line driving circuit includes a second pad separated from a first pad, the first pad being applied with...
7606097 Array sense amplifiers, memory devices and systems including same, and methods of operation  
A sense amplifier having an amplifier stage with decreased gain is described. The sense amplifier includes a first input/output (“I/O”) node and a second complementary I/O node. The sense...
7606095 Semiconductor memory device having a precharge voltage supply circuit capable of reducing leakage current between a bit line and a word line in a power-down mode  
A precharge voltage supply circuit and a semiconductor memory device using the same are described. The precharge voltage supply circuit includes a first voltage supplier configured to reduce a...
7606094 Semiconductor memory device and control method thereof  
A semiconductor memory device of the invention has memory cells arranged at intersections of bit lines and word lines, and comprises a sense amplifier for amplifying a minute potential difference...
7606093 Optimized charge sharing for data bus skew applications  
A circuit and method provide a charge sharing function during skewed data bus conditions in an integrated circuit memory. The charge sharing circuit includes two additional circuit blocks, one...
7606088 Sense amplifier circuit  
The disclosed embodiments relate to an equalization circuit, which may include a first sense amplifier having an input, the input being electrically isolated from an input to a second sense...
7606075 Read operation for NAND memory  
Non-volatile memory devices utilizing a NAND architecture are adapted to perform read operations where a first potential is supplied to source lines associated with a selected block of an array of...
7606057 Metal line layout in a memory cell  
A memory cell includes polysilicon gates 2 running in a first direction. A sequence of layers metal lines includes a layer of bit lines 4 running in a second direction substantially orthogonal...
7603493 Dynamically setting burst length of memory device by applying signal to at least one external pin during a read or write transaction  
One or more external control pins and/or addressing pins on a memory device are used to set one or both of a burst length and burst type of the memory device.
7602632 Multi-level memory cell utilizing measurement time delay as the characteristic parameter for level definition  
A method for operating a memory cell. Memory cells represent binary values by storing a characteristic parameter. The method of memory cell operation entails receiving a binary value to be stored...
7602631 Multi-level memory cell utilizing measurement time delay as the characteristic parameter for level definition  
A memory array and computer program product for operating a memory cell and memory array. An embodiment of the invention entails receiving a binary value to be stored by a memory cell. A...
7599238 Semiconductor memory device and driving method thereof  
A semiconductor memory device, for performing a writing operation faster without expanding a driver for the writing operation, includes a bit line sense amplifier (BLSA) for sensing and amplifying...
7599237 Memory device and method for precharging a memory device  
A memory device having a short precharge time is included. The memory device selects at least two pairs of bit lines and connects the selected two pairs of bit lines to the sense amplifier within a...
7599212 Method and apparatus for high-efficiency operation of a dynamic random access memory  
The disclosure generally relates to a method and apparatus for reading and writing information to a memory cell in communication with a word line and one of a bit line or a complementary bit line....
7599167 Active balancing circuit modules, systems and capacitor devices  
Circuit modules, systems and devices for controlling voltages across capacitors.
7596040 Methods and apparatus for improved write characteristics in a low voltage SRAM  
Methods and apparatus provide for writing data into and reading data from an anti-parallel storage circuit of an SRAM memory cell via a true bit line (BLT) and a complementary bit line (BLC); and...
7596035 Memory device bit line sensing system and method that compensates for bit line resistance variations  
Systems, devices and methods are disclosed, such as a system and method of sensing the voltage on bit lines that, when respective memory cells coupled to the bit lines are being read that...
7593282 Memory core with single contacts and semiconductor memory device having the same  
A memory core includes a first sub-memory array including a plurality of first memory cells, a second sub-memory array including a plurality of second memory cells, a bit line amplification circuit...
7590022 Electric fuse circuit providing margin read function  
An electric fuse circuit including a first nonvolatile memory cell connected to a first bit line, a second nonvolatile memory cell connected to a second bit line, a latch connected to the first and...
7590019 Low voltage data path and current sense amplifier  
Methods, circuits, devices, and systems are provided, including a low voltage data path and current sense amplifier. One data path includes a local input/output (LIO) line and a global input/output...
7590017 DRAM bitline precharge scheme  
Circuits and method for precharging a pair of complementary bitlines in a dynamic random access memory (DRAM). Both bitlines are precharged to VDD during a precharge phase, and during a sensing...
7586802 Memory, bit-line pre-charge circuit and bit-line pre-charge method  
A memory is provided. The memory includes a memory cell, a clamp transistor, an inverter, a bit line, a pre-charge path and a detector and controller circuit. The memory is coupled to the clamp...
7586791 Delay circuit for controlling a pre-charging time of bit lines of a memory cell array  
A semiconductor memory device includes an array of memory cells and an adjustment circuit for adjusting the pulse width of an address transition detect equalizer (ATDEQ) signal. The adjustment...
7583180 Semiconductor device for passive RFID, IC tag, and control method thereof  
A semiconductor according to an embodiment of the invention has a supply voltage generator circuit generating a supply voltage based on a received radio signal, a voltage detector circuit detecting...
7580305 Semiconductor memory  
A semiconductor memory includes: first and second bit lines; a precharge circuit for precharging the first and second bit lines to a predetermined potential; a plurality of memory cells each...
7580304 Multiple bus charge sharing  
A charge-sharing circuit includes a first input bus pair, a second input bus pair, and an output bus pair. A capacitor is coupled between a first internal node and a second internal node. A first...
7580303 Semiconductor memory having a precharge voltage generation circuit for reducing power consumption  
A precharge voltage generating circuit outputs any of a plurality of kinds of precharge voltages in accordance with an ambient temperature. A precharge circuit supplies the precharge voltage to a...
7579821 Voltage generator  
A voltage generator includes a bias signal generator generating first to fourth bias signals using a reference voltage, the first to fourth bias signals having different voltage levels. A driving...
7577785 Content addressable memory with mixed serial and parallel search  
A mixed serial-parallel content addressable memory (CAM) includes serial CAM cells and parallel CAM cells that are arranged in multiple (N) columns and multiple (M) rows. Each row includes at least...
7577046 Circuit and method for generating column path control signals in semiconductor device  
A circuit for generating column path control signals in a semiconductor device is provided. The circuit includes a strobe signal delay unit configured to receive a strobe signal, and delay the...
7577033 Method and circuit for performing read operation in a NAND flash memory  
Disclosed is a method and semiconductor circuit for providing a read operation in a NAND flash memory. The NAND flash memory includes an array of bit lines. The method includes selecting a first...
7573756 Sense amplifiers and semiconductor memory devices for reducing power consumption and methods for operating the same  
In a sense amplifier, a current amplifier outputs a first and a second voltage signal in response to a first control signal. The first and second voltage signals are output based on a detected...
7570538 Method for writing to multiple banks of a memory device  
In a multi-bank memory system such as a synchronous dynamic random access memory (SDRAM), a method of writing data to the banks is provided. This method allows for writing to any number of banks....
7570528 Precharge voltage supply circuit and semiconductor device using the same  
A precharge voltage supply circuit and a semiconductor device using the same are disclosed. The semiconductor device includes a first comparator for comparing a precharge voltage with a first...
7570527 Static random-access memory having reduced bit line precharge voltage and method of operating the same  
A bit line precharge circuit, a method of precharging a bit line and an SRAM device incorporating the circuit or the method. In one embodiment, the bit line precharge circuit includes: (1) a word...
7570507 Quasi-differential read operation  
A memory device includes an array portion of resistive memory cells comprising a plurality of bit line pairs. The device further includes a read circuit operably associated with a first charged...
7567473 Multi-level memory cell utilizing measurement time delay as the characteristic parameter for level definition  
A method for operating a memory cell and memory array. The method of memory cell operation entails receiving a request to read a binary value stored in the memory cell. A pre-charging operation...
7567468 Selective discharging memory circuit with reduced power consumption  
In memory array of a memory circuit, a discharging module and an auxiliary module are disposed on each column line. While accessing an objective memory unit on a column line of the memory, the...
7567450 Low power ROM  
A low power ROM includes a plurality of ROM core groups coupled between a plurality of word lines and bit lines, a word line decoder for selecting a desired word line of the plurality of word...
7564729 Differential and hierarchical sensing for memory circuits  
A memory circuit includes multiple word lines, multiple pairs of complementary bank bit lines, multiple block select lines, and multiple of block circuits. Each of the block circuits includes a...
7564728 Semiconductor memory device and its driving method  
A semiconductor memory device controls the voltage level of an equalization signal to be a boost voltage VPP for a predetermined time period and then to be an external power supply voltage VDD,...
7561462 Circuit and method for a high speed dynamic RAM  
An architecture, circuit and method for providing a high speed operation DRAM memory with reduced cell disturb. A DRAM global bit line select circuit couples a pair of local bit lines and the...
7558138 Bypass circuit for memory arrays  
A method for bypassing a memory array in a circuit having a global bit line, a test port configured to output a logic test, a memory portion connected to the global bit line via a word line, a...
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