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8699288 Pre-charge voltage generation and power saving modes  
A system includes a voltage generator to produce a pre-charge voltage signal for pre-charging one or more signals in a memory circuit. The one or more signals can be data bus lines used to access...
8699291 Memory circuitry with dynamic power control  
Circuits and techniques for operating a memory circuit are disclosed. A disclosed circuit includes a memory circuit and a sleep circuit with an output terminal coupled to the memory circuit. The...
8693279 Synchronous global controller for enhanced pipelining  
A system includes a memory block and a controller. The controller is adapted to skew a pre-charge signal for a bit line of the memory block. The controller can skew the pre-charge signal during a...
8693260 Memory array with two-phase bit line precharge  
An integrated circuit includes an array of memory cells with a plurality of columns and rows. A plurality of data lines is coupled to the columns in the array and a plurality of word lines is...
8687448 Semiconductor memory device and sense amplifier  
A semiconductor memory device comprises a memory cell; a first bit line and a second bit line connected to the memory cell; and a sense amplifier operative to amplify the voltage between the first...
8687447 Semiconductor memory apparatus and test method using the same  
A semiconductor memory apparatus includes: a precharge voltage control unit configured to selectively output a bit line precharge voltage or a core voltage as a control voltage in response to a...
8687459 Synchronous command-based write recovery time auto-precharge control  
Methods of operating a memory device and memory devices are provided. For example, a method of operating a memory array is provided that includes a synchronous path and an asynchronous path. A...
8681576 Pre-charge and equalization devices  
A circuit comprises a set of pre-charge and equalization devices, a control signal line, and a word line. The set of pre-charge and equalization devices is configured to pre-charge and equalize a...
8681577 Semiconductor memory integrated device having a precharge circuit with thin-film transistors gated by a voltage higher than a power supply voltage  
Provided is a semiconductor integrated device including a semiconductor memory circuit and a peripheral circuit of the semiconductor memory circuit. The peripheral circuit includes a first...
8675421 Semiconductor memory device  
A semiconductor memory device includes a first page buffer group including a plurality of page buffers coupled to memory cells of a first memory array through bit lines, a second page buffer group,...
8675439 Bit line voltage bias for low power memory design  
In a digital memory with an array of bit cells coupled to word lines and bit lines, each bit cell having cross coupled inverters isolated from bit lines by passing gate transistors until addressed,...
8675427 Implementing RC and coupling delay correction for SRAM  
A method and circuit for implementing delay correction in static random access memory (SRAM), and a design structure on which the subject circuit resides are provided. The SRAM circuit includes a...
8670284 Semiconductor device, control method thereof and data processing system  
Disclosed herein is a semiconductor device comprising a global bit line, a first local bit line coupled to normal memory cells, a second local bit line coupled to redundant memory cells first and...
8665628 Ferroelectric memory device  
A ferroelectric memory device has word, bit, plate lines; memory cells having access gate and ferroelectric capacitor; latch amplifier for latching stored data; and write amplifier for driving bit...
8659963 Enhanced power savings for memory arrays  
A memory array is provided that comprises a plurality of global bit lines such that each bit line is coupled to a plurality of memory cells. The memory array further comprises a plurality of...
8659937 Implementing low power write disabled local evaluation for SRAM  
A method and circuit for implementing low power write disabled local evaluation for Static Random Access Memory (SRAM), and a design structure on which the subject circuit resides are provided. The...
8659960 Semiconductor memory device having a data line sense amplifier  
A memory device includes a data line sense amplifier configured to receive a sense amplifying power source voltage and a sense amplifying ground voltage through a sense amplifying power source line...
8659964 Bipolar primary sense amplifier  
A sense amplifier for a memory includes two bipolar transistors and isolation switches for selectively coupling and decoupling the base of the bipolar transistors to bit lines during portions of a...
8654599 Bit line precharge circuit and a semiconductor memory apparatus using the same  
A bit line precharge circuit includes a precharge signal generation unit configured to generate first and second precharge signals that are enabled at different timing points by receiving a bit...
8649208 Method for driving semiconductor device  
A semiconductor device includes a nonvolatile memory cell including a writing transistor including an oxide semiconductor, a reading transistor including a semiconductor material different from...
8649236 Circuit and method for controlling leakage current in random access memory devices  
A circuit for controlling leakage current in random access memory devices comprises a pre-charge equalization circuit. The pre-charge equalization circuit provides a pre-charge voltage to a pair of...
8644100 Scaleable look-up table based memory  
An integrated circuit having a logic element that includes an array of storage elements convertibly functioning as either a configuration random access memory (CRAM) or a static random access...
8644091 Low voltage sensing scheme having reduced active power down standby current  
A low voltage sensing scheme reduces active power down standby leakage current in a memory device. A clamping device or diode is used between a Psense amplifier control line (e.g. ACT) and Vcc...
8644101 Local sense amplifier circuit and semiconductor memory device including the same  
A local sense amplifier circuit in a semiconductor memory device, the local sense amplifier circuit including a local data sensing unit configured to amplify a voltage difference between a local...
8644087 Leakage-aware keeper for semiconductor memory  
A circuit includes a first circuit configured to sense a leakage of a first bit line and output a first signal in response, and a second circuit configured to receive the first signal output from...
8644089 Semiconductor memory device  
A semiconductor memory device selecting a half page based on a particular bit of a row address includes: an input unit for receiving the particular bit; a control signal generation unit for...
8638621 Semiconductor memory device having a hierarchical bit line scheme  
A semiconductor memory device including a bit line connected to a memory cell and a sense amplifier configured to drive a voltage level of a global bit line in response to a voltage level of the...
8638583 Content addressable memory  
An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a...
8630138 Memory system including semicondutor memory for decoupling bad memory block from sense amplifier in standby period  
Each memory block has a plurality of memory cells, and word lines and bit lines connected to the memory cells. Precharge switches connect the bit lines to a precharge line. A switch control circuit...
8630139 Dual power supply memory array having a control circuit that dynamically selects a lower of two supply voltages for bitline pre-charge operations and an associated method  
Disclosed is a memory array in which the lower of two supply voltages from two power supplies is dynamically selected for bitline pre-charge operations. In the memory array, a voltage comparator...
8625373 Voltage shifting sense amplifier for SRAM VMIN improvement  
A sense amplifier for a SRAM device includes a PMOS differential pair and an NMOS differential pair to support operation with bit line precharge voltage as low as a few hundred millivolts without...
8625355 Semiconductor memory device and method of operating the same  
A semiconductor memory device operate during a program verification operation to apply a read voltage to a word line and a pre-charge voltage to a bit line in order to provide output data. A number...
8619477 Two-port SRAM write tracking scheme  
A Static Random Access Memory (SRAM) includes at least two memory cells sharing a read bit line (RBL) and a write bit line (WBL). Each memory cell is coupled to a respective read word line (RWL)...
8619463 Adaptive write bit line and word line adjusting mechanism for memory  
A memory including a capacitor coupled to a write bit line or a word line and an initializer configured to initialize a voltage level at a first node between the capacitor and the write bit line or...
8619482 Programmable precharge circuitry  
Integrated circuits with memory circuitry are provided. The memory circuitry may include rows of data line segments. Each data line segment may have associated memory cells, a programmable-strength...
8619483 Memory circuits, systems, and methods for accessing the memory circuits  
A memory circuit includes at least one memory cell for storing a charge representative of a datum. The memory cell is coupled with a word line and a bit line. A sense amplifier is coupled with the...
8611164 Device and method for detecting resistive defect  
The invention provides a device and method for detecting a resistive defect in a static random access memory (SRAM) device. A first aspect of the invention provides a static random access memory...
8611132 Self-body biasing sensing circuit for resistance-based memories  
A resistance based memory sensing circuit has reference current transistors feeding a reference node and a read current transistor feeding a sense node, each transistor has a substrate body at a...
8605521 Sense amplifiers, memories, and apparatuses and methods for sensing a data state of a memory cell  
Sense amplifiers, memories, and apparatuses and methods for sensing a data state of a memory cell are disclosed. An example apparatus includes a differential amplifier configured to amplify a...
8605526 Memory reliability verification techniques  
Rather than merely carrying out a BIST test by verifying whether a memory cell accurately stores a “1” or “0” under normal read/write conditions, aspects of the present discloser relate to BIST te...
8605528 Sense amplifier having an isolated pre-charge architecture, a memory circuit incorporating such a sense amplifier and associated methods  
Disclosed are a sense amplifier and a memory circuit that incorporates it. The amplifier comprises cross-coupled inverters, each with a pull-down transistor and a pull-up transistor connected in...
8605478 Semiconductor device  
In a sense circuit for DRAM memory cell a switch is provided between the bit line BL and local bit line LBL connected to the memory cells for isolation and coupling of these bit lines. The bit line...
8605530 Sense amplifier using reference signal through standard MOS and DRAM capacitor  
A memory circuit includes a first memory cell node capacitor, a first memory cell node transistor, a second memory cell node having a second memory cell node capacitor and a second memory cell node...
8599628 Precharge signal generation circuit, semiconductor device including the same, and method for generating precharge signal  
A precharge signal generation circuit includes a control signal generation unit configured to activate a control signal in response to a read command or write command and a precharge signal...
8599633 Method for reducing standby current of semiconductor memory device  
A semiconductor memory device includes memory cells, a sensing amplifier, a precharge circuit, and a control signal generator. The precharge circuit has a NMOS transistor and two PMOS transistors,...
8593867 Flash memory device and reading method thereof  
A flash memory device wherein off cell margin is increased by controlling a voltage of a sensing node and a corresponding reading method, wherein the flash memory device includes a memory cell...
8593896 Differential read write back sense amplifier circuits and methods  
A differential read write back sense amplifier circuit and corresponding methods. A memory array comprises a plurality of memory cells arranged in rows and columns; a plurality of read word lines...
8588021 Sense amplifier apparatus and methods  
Some embodiments include apparatus and methods having a sense amplifier unit, a supply node to receive a supply voltage, and a line coupled to a memory cell of a device. The sense amplifier unit...
8587990 Global bit line restore by most significant bit of an address line  
An SRAM circuitry having SRAM cells for storing at least one data word of a length of at least one bit is provided. Each bit of the data words is stored in an assigned SRAM cell, wherein the SRAM...
8588019 Semiconductor device having current change memory cell  
A semiconductor device comprises a first transistor connected between a bit line and a sense node, and a second transistor amplifying a signal of the sense node. A first potential applied to a gate...