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7619946 Active driver for use in semiconductor device  
An active driver includes an internal voltage supply node, an internal voltage generator, and a test internal voltage driving circuit. The internal voltage generator generates an internal voltage...
7619943 Circuit and method for controlling self-refresh cycle  
The present invention relates to a circuit and a method for controlling a self-refresh cycle of a dynamic random access memory or DRAM. A cell voltage is directly detected so that a self-refresh...
7619938 Repairing advanced-memory buffer (AMB) with redundant memory buffer for repairing DRAM on a fully-buffered memory-module  
A repairing fully-buffered memory module can have memory chips with some defects such as single-bit errors. A repair controller is added to the Advanced Memory Buffer (AMB) on the memory module....
7619937 Semiconductor memory device with reset during a test mode  
A semiconductor memory device performs a reset operation at a wafer state by using a signal input through an address pin in a test mode. The semiconductor memory device includes a buffer for...
7619936 System that prevents reduction in data retention  
One embodiment of the present invention provides a system including a tester and a back end manufacturing system. The tester tests a resistive memory and obtains configuration data for the...
7617425 Method for at-speed testing of memory interface using scan  
A method and a circuit of testing of a memory interface associated with an embedded memory in a semiconductor circuit involves writing to two memory locations in succession; reading the two memory...
7616509 Dynamic voltage adjustment for memory  
A power supply voltage for a memory on an integrated circuit is dynamically adjusted during the operating of the memory. The operating of the memory includes powering the memory at a supply...
7613968 Device and method for JTAG test  
In order to realize a JTAG test of a printed board including a semiconductor device having JTAG test unsupported input/output terminals inside thereof, one device is logically divided into two...
7613960 Semiconductor device test apparatus and method  
There is provided a semiconductor test apparatus which uses a test processor to apply a test signal to a DUT having a semiconductor device within it to determine whether the memory is acceptable or...
7613031 System, apparatus, and method to increase read and write stability of scaled SRAM memory cells  
Circuits, systems, and methods are disclosed for SRAM memories. An SRAM includes memory cells wherein read stability and write stability can be modified by adjusting a well bias signal operably...
7610532 Serializer/de-serializer bus controller interface  
An application specific integrated circuit (ASIC) uses a dedicated interface between core logic and an independent Serializer/De-serializer bus (SBus) to provide SBus capabilities to the core...
7610528 Configuring flash memory  
A system for configuring or testing memory may cycle a memory array while substantially concurrently performing other functional testing. In particular implementations, the system may configure, or...
7610525 Defective memory block identification in a memory device  
During manufacture and testing of a memory device, a memory test is performed to determine which, if any, memory blocks are defective. A memory map of the defective blocks is stored in one of the...
7610523 Method and template for physical-memory allocation for implementing an in-system memory test  
An in-system memory testing method includes transparently selecting and “stealing” a portion of memory from the memory system for running memory tests, then running one or more of the numerous...
7610423 Service interface to a memory system  
A cascaded interconnect system for providing a service interface to a memory system. The cascaded interconnect system includes a master service interface module, a service interface bus, and one or...
7609543 Method and implementation of stress test for MRAM  
Voltage and current stress for magnetic random access memory (MRAM) cells can weed out potential early failure cells. Method and circuit implementation of such a stress test for a MRAM comprise...
7607055 Semiconductor memory device and method of testing the same  
A semiconductor memory device includes at least one first built in self test (BIST) circuit configured to generate test pattern data, and at least one second BIST circuit configured to receive the...
7606103 Semiconductor memory device for controlling reservoir capacitor  
A semiconductor memory device is provided. Especially, there is disclosed a technique capable of increasing a net die by employing a cell capacitor as a reservoir capacitor according to a set mode....
7606092 Testing for SRAM memory data retention  
A method of testing a memory cell includes generating a logic low signal, generating a logic high signal, reducing the logic high signal to a level corresponding to the logic low signal plus an...
7606091 Method for non-volatile memory with reduced erase/write cycling during trimming of initial programming voltage  
High performance non-volatile memory devices have the programming voltages trimmed for individual types of memory pages and word lines. A group of word lines within each erasable block of memory...
7606077 Non-volatile memory with reduced erase/write cycling during trimming of initial programming voltage  
High performance non-volatile memory devices have the programming voltages trimmed for individual types of memory pages and word lines. A group of word lines within each erasable block of memory...
7605434 Semiconductor memory device to which test data is written  
A semiconductor memory device of this invention includes a first bank, a second bank, and a bank decoder that selects a bank to be activated from the first and second banks. When testing operations...
7603603 Configurable memory architecture with built-in testing mechanism  
A configurable memory architecture includes a built-in testing mechanism integrated in said memory to support very efficient built-in self-test in Random Access Memories (RAMs) with greatly reduced...
7603596 Memory device capable of detecting its failure  
A memory device capable of detecting its failure, the memory device includes a data input section for receiving data applied from an external part of the memory device; a latch section for...
7603595 Memory test circuit and method  
A memory test circuit according to an embodiment of the invention executes a test on a memory in accordance with a pattern mode signal designating a sub-test pattern included in a test pattern and...
7603592 Semiconductor device having a sense amplifier array with adjacent ECC  
A semiconductor memory device capable of achieving a sufficient operating margin without increasing an area penalty even in the case of miniaturization is provided. An error correction system...
7603493 Dynamically setting burst length of memory device by applying signal to at least one external pin during a read or write transaction  
One or more external control pins and/or addressing pins on a memory device are used to set one or both of a burst length and burst type of the memory device.
7603246 Data interface calibration  
Embodiments for positioning transitions in one or more data signals in relation to a data strobe signal are disclosed. For an example embodiment, a receiving device may return a test value to a...
7600167 Flip-flop, shift register, and scan test circuit  
A flip-flop has a first latch and a second latch. The first latch has a first feedback circuit and a first selecting circuit which selects one of a first data input signal and an output signal of...
7599242 Test circuit for multi-port memory device  
A semiconductor memory device includes a read bus line for transferring read data; a write bus line for transferring write data; and a temporary data storage unit connected between the read bus...
7599236 In-circuit Vt distribution bit counter for non-volatile memory devices  
Integrated testing components and testing algorithm on a non-volatile memory module provide faster Vt (threshold voltage) distributions during the module verification process. The memory module...
7599235 Memory correction system and method  
An error correction system and method operable to identify and correct a memory module disposed within a computer memory system. In one embodiment, the memory system comprises a first memory module...
7599206 Non-volatile semiconductor storage device  
A non-volatile semiconductor storage device includes: one or more memory cells including anti-fuse elements capable of writing data by breaking down a gate insulation film of a MOS transistor with...
7598749 Integrated circuit with fuse programming damage detection  
An integrated circuit with an efuse having an efuse link includes a damage detection structure disposed in relation to the efuse so as to detect damage in the IC resulting from programming the...
7596729 Memory device testing system and method using compressed fail data  
A memory device testing system includes a signal generator providing memory command, address and write data signal to write data in a memory device and then read the data from the memory device....
7596728 Built-in self repair circuit for a multi-port memory and method thereof  
A built-in self repair (BISR) circuit for a multi-port memory and a method thereof are provided. The circuit includes a test-and-analysis module (TAM) and a defect locating module (DLM) coupled to...
7596042 Semiconductor memory device having a plurality of chips and capability of outputting a busy signal  
One package contains a plurality of memory chips. Each memory chip has an I/O terminal which generates a busy signal. The busy signal enables a busy state when a power supply voltage value reaches...
7594148 Apparatus and method for testing semiconductor memory device  
A semiconductor memory device for performing a reliability test includes a write driving block for generating a predetermined test voltage in a test mode and delivering a data inputted from an...
7593274 Semiconductor integrated circuit and relief method and test method of the same  
A semiconductor integrated circuit is disclosed, which includes a plurality of memory circuits in which defective columns are relievable, mounted on one chip, each of the memory circuits having a...
7590903 Re-configurable architecture for automated test equipment  
An adaptive test system includes one or more reconfigurable test boards, with each test board including at least one re-configurable test processor. The re-configurable test processors can transmit...
7590900 Flip flop circuit & same with scan function  
A pulse-based flip flop, which outputs a scan input signal and a data signal, may include: a pulse generator to generate a pulse signal for coordinating operation of the flip flop; a multiplexer to...
7590023 Semiconductor memory device with internal voltage generator and method for driving the same  
A semiconductor memory device can stably supply a high voltage even if not only the PVT (Process, Voltage, and Temperature) fluctuations but also the level fluctuations of the external voltage are...
7590022 Electric fuse circuit providing margin read function  
An electric fuse circuit including a first nonvolatile memory cell connected to a first bit line, a second nonvolatile memory cell connected to a second bit line, a latch connected to the first and...
7590016 Integrated circuit  
An integrated circuit that enables a reduction in chip size and test time. This integrated circuit comprises an internal circuit; an external memory control circuit for inputting read data from an...
7587645 Input circuit of semiconductor memory device and test system having the same  
An input circuit of a semiconductor memory device includes a data input circuit and a data pattern setting circuit. The data input circuit receives first data, and generates second data by...
7586804 Memory core, memory device including a memory core, and method thereof testing a memory core  
A memory core and method thereof are provided. The example memory core may include an edge sub-array including a plurality of word lines, a plurality of bit lines, and a plurality of dummy bit...
7586801 Multi-port semiconductor memory device  
A semiconductor memory device includes: a plurality of ports configured to perform a serial input/output (I/O) data communication with external devices; a plurality of banks configured to perform a...
7586788 Nonvolatile semiconductor memory having voltage adjusting circuit  
Nonvolatile evaluation memory cells are programmed to be a plurality of different values in advance, respectively. An internal voltage generating circuit can change the value of an internal voltage...
7583557 Multi-port memory device with serial input/output interface and control method thereof  
A semiconductor memory device includes plural ports for transmitting an input data serial-interfaced with an external device into a global data bus, plural banks for parallel-interfacing with the...
7580302 Parallel threshold voltage margin search for MLC memory application  
A method for determining read voltage margins in a memory array compares as-read sum codes generated from data read from the memory array with expected sum codes generated from the loaded data. The...
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