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7378863 Synchronous semiconductor device, and inspection system and method for the same  
The present invention provides a synchronous semiconductor device suitable for improving the efficiency of application of electrical stresses to the device, an inspection system and an inspection...
7379361 Fully-buffered memory-module with redundant memory buffer in serializing advanced-memory buffer (AMB) for repairing DRAM  
A repairing fully-buffered memory module can have memory chips with some defects such as single-bit errors. A repair controller is added to the Advanced Memory Buffer (AMB) on the memory module....
7376026 Integrated semiconductor memory having sense amplifiers selectively activated at different timing  
An integrated semiconductor memory includes a memory cell array in which first sense amplifiers are arranged on a right-hand side of the memory cell array and second sense amplifiers are arranged...
7376036 Semiconductor device including fuse and method for testing the same capable of suppressing erroneous determination  
In a method for testing whether or not a fuse on a semiconductor substrate is disconnected, a first test operation is performed upon the fuse by determining whether or not a resistance value of the...
7376889 Memory device capable of detecting its failure  
A memory device capable of detecting its failure, the memory device includes a data input section for receiving data applied from an external part of the memory device; a latch section for...
7373562 Memory circuit comprising redundant memory areas  
The invention relates to a memory circuit comprising regular memory areas and redundant memory areas, redundancy circuits in each case being assigned to the redundant memory areas, each redundancy...
7372760 Semiconductor device and entry into test mode without use of unnecessary terminal  
A semiconductor device includes a first power supply terminal, a second power supply terminal, a comparison circuit coupled to the first power supply terminal and the second power supply terminal...
7372750 Integrated memory circuit and method for repairing a single bit error  
The invention relates to an integrated memory circuit having a memory cell array comprising memory cells arranged on word lines and bit lines, and having a repair circuit for repairing a single bit...
7373564 Semiconductor memory  
A normal write data selection circuit operates in the normal operation mode, and thus outputs data received through external data terminals to any one of regular cell arrays selected according to...
7372752 Test mode controller  
A test mode controller is capable of reducing a chip area and unnecessary current consumption by integrally constructing latch units of the two test circuits. The test mode controller includes a...
7372751 Using redundant memory for extra features  
Apparatus and methods are provided. A memory device has a memory array comprising primary and redundant portions. A redundancy circuit is coupled to the memory array and is coupled to receive a...
7370250 Test patterns to insure read signal integrity for high speed DDR DRAM  
A test method and implementation is described to test an internal data path within a DDR DRAM during a read operation. A worse case test sequence and a compliment of the worse case test sequence is...
7369455 Calibration circuit of a semiconductor memory device and method of operating the same  
A calibration circuit for a semiconductor device and a method of driving the same. The calibration circuit includes a PRBS generator in which a data pattern is generated within an integrated...
7369430 Adaptive algorithm for MRAM manufacturing  
Magnetic Random Access Memory (MRAM) can be programmed and read as fast as Static Random Access Memory (SRAM) and has the non-volatile characteristics of electrically eraseable programmable read...
7370249 Method and apparatus for testing a memory array  
A technique for testing a memory array. More particularly, embodiments of the invention relate to a memory array testing architecture in which a memory array within a device under test (DUT) is...
7366965 Semiconductor integrated circuit  
Test functions are expanded by adopting a self test part, and circuit scale is reduced by adding the self test part. A semiconductor integrated circuit includes a memory that includes plural memory...
RE40282 Edge transition detection circuitry for use with test mode operation of an integrated circuit memory device  
An integrated circuit structure and method provides for an integrated circuit device to respond to an edge transition detection (ETD) pulse in one of two ways. First, in response to the ETD pulse,...
7362633 Parallel read for front end compression mode  
Methods and apparatus for increasing front-end testing throughput by allowing simultaneous access to multiple banks are provided. Techniques described herein take advantage of the reduced number of...
7362632 Test parallelism increase by tester controllable switching of chip select groups  
Embodiments of the invention generally provide methods and systems for increasing the level of parallelism in testing memory devices. A set of test signals provided by a memory tester may be shared...
7362652 Semiconductor circuit  
A semiconductor circuit which includes one or plural fuse circuits being disconnectable and having a connected or disconnected state and a control circuit controlling a controlled circuit is...
7363554 Method of detecting errors in a priority encoder and a content addressable memory adopting the same  
A method of detecting errors in a priority encoder and a content addressable memory (CAM) adopting the same are provided. The CAM includes a CAM cell array, a priority encoder, and a shift register...
7362634 Built-in system and method for testing integrated circuit timing parameters  
A built-in self-test system for a dynamic random access memory device using a data output register of the memory device to apply test signals to data bus terminals and a data strobe terminal of the...
7362622 System for determining a reference level and evaluating a signal on the basis of the reference level  
A circuit exhibits a signal input, means for determining a reference level on the basis of properties of a signal received at the signal input. In addition, the circuit further exhibits means for...
7363556 Testing apparatus and testing method  
A testing apparatus for testing a memory-under-test includes a writing section for writing preset test data into each page of said memory-under-test to test said memory-under-test and a fail memory...
7359265 Data flow scheme for low power DRAM  
Circuits and methods to minimize power required for sensing and precharge of DRAMs have been achieved. A control circuit ensures that during READ operations the duration of sensing of DRAM cell and...
7359261 Memory repair system and method  
An IC includes a memory module that stores at least one of data and code. A memory repair database stores data relating to defective memory addresses. A memory control module communicates with the...
7360128 Method of testing memory device  
A test method of a memory device equipped with an internal signal generating circuit which generates an internal signal with a fixed cycle asynchronous with a signal from the outside is disclosed...
7360129 Simultaneous switch test mode  
The present invention provides a simultaneous switching (SS) test mode. SS test modules supporting an SS test mode are provided. When SS test mode is enabled, SS test mode data is driven on a data...
7359262 Semiconductor memory device  
A semiconductor memory device according to the present invention where the entire memory area determined by an array of memory cells is divided into a plurality of memory areas comprises at least...
7359260 Repair of memory cells  
A memory device has at least one sub array of memory cells having data columns and at least one spare sub array having spare columns. In one embodiment the sub array of memory cells and the sub...
7359263 Chip information managing method, chip information managing system, and chip information managing program  
In replacing word lines having defective addresses with redundant word lines, information is held in a relationship between the word lines and the redundant word lines. In other words, information...
7359268 Semiconductor memory device for low voltage  
A semiconductor memory device includes a read amplifying unit for transferring a data from a local data line pair to a global data line as a read data; a write driver for transferring a write data...
7355878 Programmable logic devices optionally convertible to one time programmable devices  
Programmable logic devices (PLDs) that can be repeatedly erased and reprogrammed, e.g., during the testing and/or design phases, and then converted to one-time programmable (OTP) devices on a...
7356743 RRAM controller built in self test memory  
An RRAM design having linear BIST memory and rectangular BIST memory, the improvement comprising at least one of the linear BIST memory and the rectangular BIST memory formed only of flipflops and...
7356741 Modular test controller with BIST circuit for testing embedded DRAM circuits  
A modular test controller with a built-in self-test (BIST) circuit for testing an embedded DRAM (eDRAM) circuit is provided. The test controller includes a built-in self-test (BIST) core for...
7355901 Synchronous output buffer, synchronous memory device and method of testing access time  
An output buffer includes an output terminal, a pull up module, a pull down module and an output latching module. The pull up module pulls up the output terminal to a first source voltage when the...
7352639 Method and apparatus for increasing yield in a memory circuit  
Apparatus for repairing one or more shorted memory cells in a memory circuit includes control circuitry. The control circuitry is operative in one of at least a first mode and a second mode. In the...
7353442 On-chip and at-speed tester for testing and characterization of different types of memories  
An on-chip and at-speed tester for testing and characterization of different types of memories in an integrated circuit device, comprising a Centralized Flow Controller for automatically...
7352638 Method and apparatus for testing a memory device  
The extension sector enable signal RS_SEL is a test target control signal for switching a test target between ordinary sectors and redundant sectors. During the test period of redundant sectors, if...
7349271 Cascaded test circuit with inter-bitline drive devices for evaluating memory cell performance  
A cascaded test circuit with inter-bitline drive devices for evaluating memory cell performance provides for circuit delay and performance measurements in an actual memory circuit environment. A...
7349272 Multi-port semiconductor memory device  
A semiconductor memory device includes: a plurality of ports configured to perform a serial input/output (I/O) data communication with external devices; a plurality of banks configured to perform a...
RE40172 Multi-bank testing apparatus for a synchronous dram  
A multi-bank testing apparatus for a synchronous DRAM, which allows all banks of the synchronous DRAM to simultaneously carry out their write and read operations in a test mode, thereby being...
7349283 Integrated semiconductor memory  
An integrated semiconductor memory includes a test mode control circuit and at least one voltage generator for generating an operating voltage that is fed into memory banks via interconnects....
7349253 Memory device and method for testing memory devices with repairable redundancy  
A memory device and method for testing memory devices with repairable redundancy is disclosed. In one embodiment, both the regular memory area and the redundant memory area are subject to the same...
7349246 Initial firing method and phase change memory device for performing firing effectively  
In a firing method of a phase change memory device and a phase change memory capable of effectively performing a firing operation, the phase change memory device includes a plurality of memory cell...
7348596 Devices for detecting current leakage between deep trench capacitors in DRAM devices  
A test device for detecting current leakage between deep trench capacitors in DRAM devices. The test device is disposed in a scribe line region of a wafer. In the test device, a first trench...
7349273 Access circuit and method for allowing external test voltage to be applied to isolated wells  
An access circuit selectively couples an externally accessible terminal to each of a plurality of isolated DRAM wells in which respective DRAM arrays are fabricated. The access circuit for each...
7350119 Compressed encoding for repair  
A hierarchical encoding format for coding repairs to devices within a computing system. A device, such as a cache memory, is logically partitioned into a plurality of sub-portions. Various portions...
7346815 Mechanism for implementing redundancy to mask failing SRAM  
In some embodiments, an apparatus to implement redundancy for failure masking in memory is disclosed. The apparatus comprises a built-in self test (BIST) log to store BIST data representing faulty...
7345935 Semiconductor wafer and method for testing ferroelectric memory device  
A semiconductor wafer includes a plurality of semiconductor chip regions including ferroelectric memory devices, a test chip region, and a wiring that connects each of the plurality of...
Matches 351 - 400 out of 2995 < 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >