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7167404 |
Method and device for testing configuration memory cells in programmable logic devices (PLDS)
A programmable logic device (PLD) has the ability to test the configuration memory either independently or during configuration. The PLD may include a selector for selecting a particular column or...
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7167405 |
Data transfer verification systems and methods
Systems and methods are directed to verification of configuration data stored in memory cells. For example, in one embodiment, an integrated circuit includes a first plurality of memory cells...
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7168018 |
Apparatus and method for reducing test resources in testing DRAMs
An apparatus and a method are disclosed for reducing the pin driver count required for testing computer memory devices, specifically Rambus DRAM, while a die is on a semiconductor wafer. By...
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7164613 |
Flexible internal address counting method and apparatus
A method of controlling an internal address counter which provides a count used in accessing a storage cell array to provide increased flexibility in the performance of a test on the array,...
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7164612 |
Test circuit for measuring sense amplifier and memory mismatches
Post-manufacture compensation for a sensing offset can be provided, at least in part, by selectively exposing one of a pair of cross-coupled transistors in a sense amplifier to a bias voltage...
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7161857 |
Memory redundancy programming
A method and apparatus is provided for performing a redundancy programming. The system of the present invention includes a device testing unit for performing a memory test. The system also includes...
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7161866 |
Memory device tester and method for testing reduced power states
A memory device tester capable of testing for proper operation of reduced power states in memory devices. The memory device tester can include a processor or a state machine, each configured to...
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7162669 |
Apparatus and method for compressing redundancy information for embedded memories, including cache memories, of integrated circuits
An embedded memory on an integrated circuit has a memory cell array equipped with replacement cells and mapping logic for electronically substituting the replacement cells for defective cells at at...
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7162660 |
Semiconductor memory and method of testing the same
A memory section includes an array of a plurality of memory elements, an address selecting circuit, a data selecting circuit having a data writing section for being driven for writing or reading...
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7158426 |
Method for testing an integrated semiconductor memory
An integrated semiconductor memory can be operated in a normal operating state synchronously with a control clock. In the test operating state, the integrated semiconductor memory is driven...
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7158407 |
Triple pulse method for MRAM toggle bit characterization
A method is provided for testing magnetic bits ( 3, 104, 514 ) of an array. A train of first ( 702 ), second ( 704 ), and third ( 706 ) pulses is provided to a desired bit, the first and second...
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7158415 |
System for performing fast testing during flash reference cell setting
An embedded circuit in a memory device is used in place of an external test device to perform time-consuming tasks such as voltage verification during the setting of reference cells. An external...
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7159156 |
Memory chip with test logic taking into consideration the address of a redundant word line and method for testing a memory chip
A memory chip includes an on-chip data generator, a scrambler unit for checking the correct operability of the memory cells, a repair unit, and redundant word lines that, in the case of a memory...
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7159157 |
Apparatus and method for testing a device for storing data
The present invention provides an apparatus for testing a device ( 102 ) for storing data, which has a device for comparing actual data with set point data for individual storage areas and a device...
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7155645 |
System and method for testing memory while an operating system is active
A system for testing a memory page of a computer while an operating system is active. The system includes a hook function and a pattern generator. The hook function has software instructions that...
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7155643 |
Semiconductor integrated circuit and test method thereof
A semiconductor integrated circuit includes a memory which has redundant lines for repair in both a column direction and a row direction. A test pattern generating section generates a specific test...
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7154793 |
Integrated memory and method for functional testing of the integrated memory
An integrated memory includes memory cells arranged in a memory cell array along word lines and bit lines. One of the bit lines can be connected to a data line by a respective one of a plurality of...
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7154808 |
Semiconductor memory device for simultaneously testing blocks of cells
A semiconductor memory device comprises a plurality of cell blocks, block controllers for activating or precharging word lines of each of the cell blocks according to an external active command and...
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7154794 |
Memory regulator system with test mode
A system for switching between a read mode and a write mode. The system includes a voltage regulating circuit and a memory array. The voltage regulating circuit includes a voltage input and a...
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7154790 |
Multi-chip semiconductor packages and methods of operating the same
Integrated circuit devices are provided including first and second chips and a common input/output pad electrically coupled to the first and second chips. At least one of the first and second chips...
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7151705 |
Non-volatile memory device architecture, for instance a flash kind, having a serial communication interface
The present invention relates to a non volatile memory device architecture, for example of the Flash type, incorporating a memory cell array and an input/output interface to receive memory data...
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7152192 |
System and method of testing a plurality of memory blocks of an integrated circuit in parallel
A method of testing a plurality of memory blocks of an integrated circuit in parallel, wherein each memory block comprising data bit storage cells in an array of rows and columns, and wherein each...
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7151713 |
Semiconductor memory device
A semiconductor memory device has a command decoder responsive to a plurality of commands to set the semiconductor memory device to a normal mode, for generating control signals corresponding to...
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7152187 |
Low-power SRAM E-fuse repair methodology
A low power E-fuse repair methodology substantially removes system latency during memory and/or E-fuse farm module power-down in a device that employs E-fuse farm technology. The method maintains...
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7149824 |
Dynamically setting burst length of memory device by applying signal to at least one external pin during a read or write transaction
One or more external control pins and/or addressing pins on a memory device are used to set one or both of a burst length and burst type of the memory device.
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7149140 |
Method of refreshing a memory device utilizing PASR and piled refresh schemes
In a memory device having an N number of banks, a refresh operation according to a piled refresh scheme is performed during a self-refresh mode to refresh the N number of banks in regular sequence...
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7149137 |
Process monitoring for ferroelectric memory devices with in-line retention test
The present invention facilitates evaluation of ferroelectric memory devices. A ferroelectric memory device is fabricated that comprises memory cells comprising ferroelectric capacitors ( 802 ). A...
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7149136 |
Memory circuit with redundant memory cell array allowing simplified shipment tests and reduced power consumptions
A memory circuit has a regular memory cell array; a redundant memory cell array that can replace a failed portion in the regular memory cell array; a redundant replacement memory for storing data...
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7149941 |
Optimized ECC/redundancy fault recovery
A fault recovery system for an array of memory cells. A register stores data indicating addresses of multi-cell fails and single-cell fails. A first fault correction system accesses data from the...
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7145797 |
Selecting a magnetic memory cell write current
The invention includes an apparatus and method for selecting a desirable magnitude of a magnetic memory cell write current. The method includes determining a minimal magnitude of write current for...
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7145818 |
Semiconductor integrated circuit device having test circuit
A semiconductor integrated circuit device is provided with a diagnosis circuit, which does not increase the delay of a logic element in normal operation. In a latch provided at the output of a...
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7145816 |
Using redundant memory for extra features
Apparatus and methods are provided. A memory device has a memory array comprising primary and redundant portions. A redundancy circuit is coupled to the memory array and is coupled to receive a...
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7146547 |
Semiconductor device
In a testing method for a semiconductor memory using a memory BIST process, when it is difficult to carry out a comparing process in one cycle, a pipelining process is used for an expected value...
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7143309 |
Information storage apparatus that can relocate data to be stored in defective sectors
An information storage apparatus includes a recording medium having a user region including user sectors, an alternative region having alternative sectors, and a preparatory region provided in the...
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7142472 |
Semiconductor memory device and method for testing same
A semiconductor memory device having a sense amplifier for detecting data stored in a memory cell via a bit line pair connected to the memory cell, and voltage application means, an output voltage...
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7139946 |
Method and test circuit for testing memory internal write enable
A method of testing write enable lines of random access memory having at least one word having one or more write enable inputs for controlling write operations in the word, comprises, for a...
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7139943 |
Method and apparatus for providing adjustable latency for test mode compression
An integrated circuit includes a core memory array and a test mode compression circuit. The test mode compression circuit receives test mode data from the core memory array. A multiplexer receives...
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7139204 |
Method and system for testing a dual-port memory at speed in a stressed environment
A method and system for testing a multi-port memory cell are described. According to one embodiment of the invention, a multi-port memory device comprises an array of multi-port memory cells....
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7139945 |
Chip testing within a multi-chip semiconductor package
A system and method is provided for testing a secondary chip housed within a multi-chip packaged semiconductor device. The packaged semiconductor device includes a secondary chip and a primary...
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7136315 |
Bank selectable parallel test circuit and parallel test method thereof
A parallel test circuit performs a selective test on a specific bank. The bank selectable parallel test circuit comprises a bank selecting control unit and a plurality of bank selecting units. The...
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7136316 |
Method and apparatus for data compression in memory devices
A test circuit for a memory device having a pair of arrays each of which includes a plurality of memory cells arranged in rows and columns. A pair of complementary digit lines is provided for each...
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7136314 |
Memory device and test method thereof
A memory device and a test method thereof enable verification of failure of a cell region by intercepting bit lines connected to the cell region in a write-verify-read test. The memory device...
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7136322 |
Programmable semi-fusible link read only memory and method of margin testing same
A programmable read only memory includes a matrix of semi-fusible link memory cells, each including a semi-fusible link having an intact impedance and a blown impedance; a bit line voltage supply...
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7132842 |
Semiconductor device, driving method and inspection method thereof
For an inspection of a display device which incorporates a driver circuit around pixels, a start pulse and a clock pulse are required to be inputted as inspection signals. The more complex the...
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7133320 |
Flood mode implementation for continuous bitline local evaluation circuit
A method, an apparatus, and a computer program product are provided for flood mode implementation of SRAM cells that employ a continuous bitline local evaluation circuit. Flood mode testing is used...
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7134063 |
Apparatus and method for testing on-chip ROM
An apparatus for testing an on-chip ROM and a method thereof are provided. By embedding the on-chip ROM test apparatus in a semiconductor chip and externally providing only minimal information, the...
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7133319 |
Programmable weak write test mode (PWWTM) bias generation having logic high output default mode
The present invention employs a bias voltage having a selectable magnitude to bias a weak write pull-down transistor in a write driver of a static random access memory (SRAM) array. A programmable...
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7131040 |
Manifold-Distributed Air Flow Over Removable Test Boards in a Memory-Module Burn-In System With Heat Chamber Isolated by Backplane
Hot air blown past memory modules under test in a heat chamber is improved. Hot air entering the chamber from an inlet pipe is split by a manifold and deflectors. Holes in the manifold allow for a...
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7130230 |
Systems for built-in-self-test for content addressable memories and methods of operating the same
An improved Built-In-Self-Test (BIST) architecture for Content Addressable Memory (CAM) devices, including a bit scanner for reading out the contents of the matchlines of the CAM cells as a serial...
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7130231 |
Method, apparatus, and computer program product for implementing enhanced DRAM interface checking
A method, apparatus, and computer program product are provided for implementing an enhanced DRAM interface checking. An interface check mode enables interface checking using a refresh command for a...
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