Matches 551 - 600 out of 2997 < 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 >
Match Document Document Title
7202681 Motherboard memory slot ribbon cable and apparatus  
A testing apparatus, system and method for testing computer memory modules are disclosed. The apparatus includes a motherboard having a processor and at least one resident memory socket fixed to...
7203091 Semiconductor integrated circuit device and non-volatile memory system using the same  
A semiconductor integrated circuit device includes a non-volatile memory having a pseudo pass function of returning a pass as a status even if a bit error reaching an allowable number of bits...
7203109 Device and method for detecting corruption of digital hardware configuration  
A device for verifying hardware in a circuit arrangement that includes one or more configuration elements ( 106 ) operable to configure hardware elements ( 108 ) that are electrically coupled by...
7200690 Memory access system providing increased throughput rates when accessing large volumes of data by determining worse case throughput rate delays  
Enhancing the throughput rate of a memory access system by using store and forward buffers (SFB) in combination with a DMA engine. According to an aspect of the present invention, the worst case...
7200780 Semiconductor memory including error correction function  
A semiconductor memory comprises, a data memory having a plurality of memory regions to store data at addresses specified, a code memory having the same address space as the data memory to store...
7200786 Built-in self-analyzer for embedded memory  
Methods and apparatus for analyzing memory defects in an embedded memory are described. According to certain embodiments, the analysis can be performed “at-speed” and can be used to analyze...
7200059 Semiconductor memory and burn-in test method of semiconductor memory  
A burn-in test, including first to sixth steps where voltages are applied for the same lengths of time in each step, is applied to a semiconductor memory having alternately arranged bit line pairs...
7200058 Semiconductor memory device  
A semiconductor memory device includes a memory cell array, in which a plurality of electrically rewritable and non-volatile memory cells connected in series and first and second select transistors...
7200057 Test for weak SRAM cells  
A method and apparatus for testing a static random access memory (SRAM) array for the presence of weak defects. A 0/1 ratio is first written to the memory array (step 100 ), following which the...
7197678 Test circuit and method for testing an integrated memory circuit  
A test circuit for testing a memory circuit has a data input line for providing test data and a comparator unit. The comparator unit is connected to the data input line and to the memory circuit...
7196952 Column/sector redundancy CAM fast programming scheme using regular memory core array in multi-plane flash memory device  
Programming redundant columns for a multi-plane EEPROM includes identifying a defective memory column during a back-end testing operation to provide redundancy information in the form of the...
7193917 Semiconductor storage device, test method therefor, and test circuit therefor  
A test method and a test circuit which enable operations to be checked when the time interval between a refresh operation and a read or write operation is forcibly reduced. Timings for a read or...
7193918 Process for refreshing a dynamic random access memory and corresponding device  
The content of a few pages of the dynamic random access memory is backed up, then one tries to refresh them less quickly, for example two times less quickly, and one observes whether this does or...
7193877 Content addressable memory with reduced test time  
A CAM device having internal circuitry to reduce test time through parallel test setup and parallel pass/fail result generation. A plurality of match results is generated in parallel within a...
7194667 System for storing device test information on a semiconductor device using on-device logic for determination of test results  
A system for testing a semiconductor device and storing device test results in nonvolatile memory elements on the tested device, in which the semiconductor device includes logic circuitry which...
7191379 Magnetic memory with error correction coding  
Embodiments of the present invention are implemented in memory systems. In one embodiment, the memory comprises an array of memory cells and a control circuit. The control circuit is configured to...
7190625 Method and apparatus for data compression in memory devices  
A test circuit for a memory device having a pair of arrays each of which includes a plurality of memory cells arranged in rows and columns. A pair of complementary digit lines is provided for each...
7187599 Integrated circuit chip having a first delay circuit trimmed via a second delay circuit  
An integrated circuit chip including a first delay circuit and a second delay circuit. The first delay circuit has a first delay circuit topology configured to delay a signal a first delay. The...
7187602 Reducing memory failures in integrated circuits  
Memory reliability is improved by using redundancy to repair errors detected by ECC. In one embodiment, redundancy repairs errors which cannot be corrected by ECC. The redundancy can employ the use...
7187195 Parallel compression test circuit of memory device  
A parallel compression test circuit of a memory device disperses peak current and reduce noise by operating input/output amplifiers at different timings in a parallel compression test mode. The...
7187603 Semiconductor memory device, repair search method, and self-repair method  
A semiconductor memory device according to the present invention includes a BIST circuit for evaluating quality of each of memory cells and a buffer (memory) for storing address information of...
7187604 Semiconductor memory  
A shift register includes plural latches corresponding to normal word lines of normal memory cell rows and a redundancy word line of a redundancy memory cell row, respectively, in order to...
7188291 Circuit and method for testing a circuit having memory array and addressing and control unit  
A circuit configuration for testing a circuit using a test device for providing a test mode, where test procedures are performed sequentially. The test procedures involve comparing actual data that...
7185243 Testing implementation suitable for built-in self-repair (BISR) memories  
A semiconductor memory testing implementation suitable for build-in self repair (BISR) memories provides, in one embodiment, a memory testing circuit configuration including an output register for...
7184332 Memory circuit and method for processing a code to be loaded into a memory circuit  
A ROM-type memory is provided that includes a matrix of memory cells made up of rows and columns, with each row allowing storage of a page of MUX words of N bits. An address decoder decodes...
7184339 Semi-conductor component, as well as a process for the in-or output of test data  
The invention relates to a semi-conductor component, and a process for the in- and/or output of test data and/or semi-conductor component operating control data into or from a semi-conductor...
7184324 Semiconductor memory device having a single input terminal to select a buffer and method of testing the same  
A semiconductor memory device has a single input terminal to select a buffer and includes input-output terminals, input-output buffers, a memory core, and a buffer selecting unit. The input-output...
7184336 Method and test structure for evaluating threshold voltage distribution in a memory array  
A method for evaluating threshold voltage distribution of memory cells. The method comprises connecting all sources and drains of memory cells in a memory array to a fixed voltage; measuring charge...
7184334 Semiconductor memory device and method of testing semiconductor memory device  
A semiconductor memory device comprises at least one memory plane in which a plurality of memory blocks are arranged, and a block decoder circuit which decodes a block address signal for selecting...
7184305 Nonvolatile semiconductor storage device and row-line short defect detection method  
A current-path isolating circuit is provided in a row decoder circuit that selects a part of the plurality of row lines of a memory array and that selectively provides a selected row line with a...
7184319 Method for erasing non-volatile memory cells and corresponding memory device  
The invention relates to a method for erasing non-volatile memory cells, and to a corresponding non-volatile memory device of the programmable and electrically erasable type implementing the...
7185245 Test reading apparatus for memories  
Test reading apparatus having a memory device having individual memory cells, a buffer device, which is connected to the memory device, and which stores data written to the memory cells in the...
7184338 Semiconductor device, semiconductor device testing method, and programming method  
A semiconductor device includes: a latch circuit that latches a given signal in a test mode; and a generating circuit that generates a signal that defines a program voltage used for programming of...
7184337 Method for testing an integrated semiconductor memory  
A method for testing an integrated semiconductor memory provides for disturbing memory cells arranged along a first word line by a disturbance signal on an adjacent word line. The memory cells...
7184340 Circuit and method for test mode entry of a semiconductor memory device  
A circuit and method for test mode entry of a semiconductor memory device are provided. In a method of entering a semiconductor memory device into a test mode, an internal clock is generated in...
7184335 Electronic memory apparatus, and method for deactivating redundant bit lines or word lines  
Electronic memory apparatus, and method for deactivating redundant bit lines or word lines An electronic memory apparatus ( 100 ) having a memory cell array ( 101 ), a column address decoding unit...
7180802 Method of stress-testing an isolation gate in a dynamic random access memory  
The present invention includes a DRAM array. The DRAM array includes a first memory cell, a second memory cell and an isolation gate formed between the first and second memory cells. The isolation...
7181658 Method for testing semiconductor memory device and test circuit for semiconductor memory device  
In synchronization with a PLL clock PCK having a frequency four times that of an external clock ECK, n number of internal addresses IAD including an external address EAD are generated and, in...
7177211 Memory channel test fixture and method  
Method and apparatus for use with buffered memory modules are included among the embodiments. In exemplary systems, the memory module has a host-side memory channel port and a downstream memory...
7177209 Semiconductor memory device and method of driving the same  
Provided is directed to a semiconductor memory device and a method of driving the same capable of improving a repair efficiency with comparison to the conventional method which repairs all the...
7178073 Test method and test apparatus for an electronic module  
A method for testing an electronic module having a memory cell device includes writing an information item to the memory cell device at a first clock frequency and then reading-out the information...
7178076 Architecture of an efficient at-speed programmable memory built-in self test  
A method of testing an embedded memory at speed within an integrated circuit which includes providing a memory built in self test sequencer module, providing a satellite engine module coupled to...
7173839 Large scale integrated circuit and at speed test method thereof  
Disclosed are an apparatus and a method that at-speed-test a data cache included in a semiconductor integrated circuit by means of an on-chip memory having a size smaller than that of the data...
7174489 Semiconductor memory test device  
Conventionally, when a burn-in test is performed by means of utilizing a memory BIST circuit, a control of a reset operation for the memory BIST circuit is required from an external source....
7170804 Test mode for detecting a floating word line  
Devices and methods that allow floating word lines in memory arrays to be detected are provided. By driving local word lines from each side with divided drive lines, local word lines on one side of...
7170806 Data path having grounded precharge operation and test compression capability  
A data path for coupling data between a memory cell and an input/output (IO) line sense amplifier. An IO line coupling circuit is coupled to a pair of global data lines and a pair of local data...
7170797 Test data topology write to memory using latched sense amplifier data and row address scrambling  
For one or more disclosed embodiments, a test data topology may be written to memory by writing data into an initial row of memory cells. The writing of data comprises latching data in a plurality...
7171597 Input/output compression test circuit  
The I/O compression test circuit performs test on global I/O lines divided into groups after failure occurs, thereby improving repair efficiency. The configuration of the test circuit is simplified...
7170801 Method for replacing defects in a memory and apparatus thereof  
A method and an apparatus for restoring defective memory cells are provided. The apparatus includes memory, a memory scan controller, which scans the memory to see if the memory is defective when a...
7168017 Memory devices with selectively enabled output circuits for test mode and method of testing the same  
A memory device, such as a DDR SDRAM, may be provided in which subsets of data output circuits of the device can be selectively enabled to allow sets of data output pins to be connected in common...
Matches 551 - 600 out of 2997 < 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 >