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9042191 Self-repairing memory  
A memory array has a plurality of rows including a plurality of memory words. Each first bit of a plurality of first bits is associated with a memory word of the each row. A state of the each...
9042178 Program and read trim setting  
A method and apparatus for setting trim parameters in a memory device provides multiple trim settings that are assigned to portions of the memory device according to observed or tested programming...
9036445 Semiconductor devices  
The semiconductor device includes a power source signal generator and a redundancy signal generator. The power source signal generator generates a fuse power source signal driven to have a target...
9030899 Memory device with post package repair, operation method of the same and memory system including the same  
An operation method of a memory device includes entering a repair mode, changing an input path of setting data from a set path to a repair path in response to the entering of the repair mode,...
9030897 Memory and memory system for preventing degradation of data  
A memory may comprise a first bank configured to include first to Nth word lines and first to Mth redundancy word lines to replace M number of word lines among the first to Nth word lines, a...
9030873 Semiconductor device and method of operating the same  
A method of operating a semiconductor device includes storing a supplying condition of a read voltage inputted from an external source into an internal register to perform a read operation of...
9030898 Semiconductor device  
An embodiment of the present invention provides a semiconductor, including a non-volatile storage unit suitable for storing one or more first addresses; an address storage unit suitable for...
9025406 Semiconductor integrated circuit and method of driving the same  
A semiconductor integrated circuit includes a fuse circuit comprising a fuse configured to generate a fuse state signal corresponding to a rupture state of the fuse in response to an enable...
9019786 Repair system for repairing defect using E fuses and method of controlling the same  
A system for repairing a plurality of semiconductor chips each comprising a data storage region including electric fuses connected to the data storage regions of the plurality of semiconductor...
9019791 Low-pin-count non-volatile memory interface for 3D IC  
A low-pin-count non-volatile (NVM) memory to be provided in an integrated circuit for a 3D IC to repair defects, trim devices, or adjust parameters is presented here. At least one die in a 3D IC...
9019776 Memory access circuit for double data/single data rate applications  
A memory access circuit includes a write data circuit and a first write switch circuit. The write data circuit is used for receiving double data rate data or single data rate data, and outputting...
9013936 Memory and memory system including the same  
A memory includes first to Nth word lines, first to Mth redundancy word lines configured to replace M number of word lines among the first to Nth word lines, and a control circuit configured to...
9013934 Method of operating a nonvolatile memory by reprogramming failed cells using a reinforced program pulse in an idle state and memory system thereof  
A memory system, and an operation method of a nonvolatile memory, include programming memory cells using a normal program pulse, reading out a first set of data from the memory cells, detecting...
9013937 Semiconductor device, method for inspecting the same, and method for driving the same  
A method for limiting writing of data to a specific memory cell without disconnecting a wiring of a memory cell array or placing a prober in contact with a memory cell, a row, or a column is...
9007830 Semiconductor memory device having faulty cells  
A nonvolatile memory apparatus includes a control unit, a main storage medium with an electrically reloadable nonvolatile memory adapted to be operable even when faulty memory cells exist therein,...
9007856 Repair control circuit and semiconductor memory device including the same  
A repair control circuit of controlling a repair operation of a semiconductor memory device includes a row matching block and a column matching block. The row matching block stores fail group...
9007860 Sub-block disabling in 3D memory  
Some embodiments relate to apparatuses and methods associated with blocks of memory cells. The blocks of memory cells may include two or more sub-blocks of memory cells. One such sub-block may...
9006003 Method of detecting bitmap failure associated with physical coordinate  
A method of detecting bitmap failure associated with physical coordinates is provided. In the method, data of wafer mapping inspection are obtained first, and the data include images of defects in...
9001569 Input trigger independent low leakage memory circuit  
Wordline-driver biasing and column-based source-biasing circuitry facilitate reduced current leakage, for example, in SoC device SRAM circuits in a manner that is independent of the...
9003255 Automatic test-pattern generation for memory-shadow-logic testing  
An embodiment of a method for automated test pattern generation (ATPG), a system for ATPG, and a memory configured for ATPG. For example, an embodiment of a memory includes a first test memory...
9001601 Memory device including repair circuit and repair method thereof  
A memory device includes a repair circuit including a fail bit location information table configured to store row and column addresses of a defective cell in a normal area of a memory cell array....
9001602 Method of burn-in test of EEPROM or flash memories  
A method for testing an integrated circuit includes, in a burn-in test mode, two steps during which gate oxides of conductive high voltage MOS transistors of the integrated circuit are subjected...
9001609 Hybrid latch and fuse scheme for memory repair  
A method and apparatus for managing memory in an electronic system is described. The method includes determining a failure in an element of the memory array that is repairable by a redundant...
9001567 Replacement of a faulty memory cell with a spare cell for a memory circuit  
A memory integrated circuit device is provided. The device includes a plurality of regular address inputs and at least one spare address input configured for a selected mode or an unselected mode....
9001568 Testing signal development on a bit line in an SRAM  
An embodiment of the invention discloses a method for testing a memory cell in an SRAM. The number of dummy memory cells on a single dummy word line used to drive the dummy bit lines is selected....
8996936 Enhanced error correction in memory devices  
A method of correcting stored data includes reading data stored in a portion of a nonvolatile memory. The method includes, for each particular bit position of the read data, updating a count of...
8995212 Column repair circuit  
A column repair circuit of a semiconductor memory apparatus includes a plurality of mats and performs a column repair operation to replace failed cells among a plurality of memory cells provided...
8995188 Sharing support circuitry in a memory  
A memory device, system, and method for operation of a memory device. In one such memory device, the memory device comprises a plurality of strings of memory cells. A plurality of drain select...
8995217 Hybrid latch and fuse scheme for memory repair  
A method and apparatus for managing memory in an electronic system is described. The method includes determining a failure in an element of the memory array that is repairable by a redundant...
8995196 Method of sorting a multi-bit per cell non-volatile memory and a multi-mode configuration method  
A method of sorting a multi-bit per cell non-volatile memory includes programming and reading to test an n-bit-per-cell (n-bpc) non-volatile memory, which has a plurality of m-bpc pages, where m...
8988956 Programmable memory built in self repair circuit  
An integrated circuit chip comprising at least one programmable built-in self-repair (PBISR) for repairing memory is described. The PBISR comprises an interface that receives signals external to...
8990646 Memory error test routine  
An error test routine tests for a type of memory error by changing a content of a memory module. A memory handling procedure isolates the memory error in response to a positive outcome of the...
8988964 Semiconductor memory device and refresh leveraging driving method thereof  
A refresh leveraging driving method is provided which includes deciding a unit of word lines to be driven at a refresh leveraging operation to be the same as a redundancy repair row unit setting a...
8982655 Apparatus and method for compression and decompression of microprocessor configuration data  
An apparatus is contemplated for storing and providing configuration data to a microprocessor. The apparatus has a core, disposed on a die, and a fuse array, disposed on the die and coupled to the...
8982596 Content addressable memory having column segment redundancy  
A CAM device includes a CAM array that can implement column redundancy in which a defective column segment in a selected block can be functionally replaced by a selected column segment of the same...
8976604 Method and apparatus for copying data with a memory array having redundant memory  
A page copy operation such as copy back programming is performed between a source page of the memory array and a destination page of the memory array in different segments. The segments divide the...
8977929 Rearranging write data to avoid hard errors  
This disclosure relates to avoiding a hard error in memory during write time by shifting data to be programmed to memory to mask the hard error. In one implementation, a method of programming data...
8972822 Memory module and semiconductor storage device  
A memory module includes a plurality of memory chips stacked on top of one another, each of the plurality of memory chips including a memory cell unit that is divided into a plurality of blocks,...
8971116 Semiconductor device and method of operating the same  
A semiconductor device includes a plurality of page buffers coupled to bit lines and suitable for performing a verification operation to output a verification signal to a verification terminal,...
8971137 Bit based fuse repair  
In accordance with some embodiments, instead of providing replacement rows, an area within a fuse array may be reserved for storing addresses of bits that are defective. Then these bits can be...
8971094 Replacement of a faulty memory cell with a spare cell for a memory circuit  
A memory interface device has an address input(s) configured to receive address information from an address stream of a host controller; an address output(s) configured to drive address...
8971138 Method of screening static random access memory cells for positive bias temperature instability  
A method of screening complementary metal-oxide-semiconductor CMOS integrated circuits, such as integrated circuits including CMOS static random access memory (SRAM) cells, for n-channel...
8970249 Look-up table circuit  
One embodiment provides a look-up table circuit, including: 2i memories, a half of which constituting a first memory group, the other half of which constituting a second memory group; first to...
8971136 Memory device correcting the effect of collision of high-energy particles  
A memory device automatically correcting the effect of collisions of high-energy particles, comprising at least one memory cell, and further comprising: retention means for retaining, for a...
8964495 Memory operation upon failure of one of two paired memory devices  
A method and apparatus for continued operation of a memory module, including a first and second memory device, when one of memory devices has failed. The method includes receiving a write...
8964493 Defective memory column replacement with load isolation  
Exemplary embodiments of the present invention disclose a method and system for substituting a group of memory cells for a defective group of memory cells in a memory. In a step, an exemplary...
8964494 memories and methods for repair in open digit memory architectures  
A memory with extra digit lines in full size end arrays with an open digit architecture, which can use the extra digit lines to form repair cells. In one example, folded digit sense amplifiers are...
8953398 Block level grading for reliability and yield improvement  
A system for grading blocks may be used to improve memory usage. Blocks of memory, such as on a flash card, may be graded on a sliding scale that may identify a level of “goodness” or a level of...
8947960 Semiconductor storage with a floating detection circuitry and floating detection method thereof  
A storage medium including a plurality of memory cells, a plurality of transmission lines, a driving module and a floating detection module is disclosed. The memory cells store data. The...
8947958 Latent slow bit detection for non-volatile memory  
In accordance with at least one embodiment, a non-volatile memory (NVM) and method is disclosed for detecting latent slow erase bits. At least a portion of an array of NVM cells is erased with a...