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7619438 |
Methods of enabling the use of a defective programmable device
Methods of enabling the use of defective programmable devices. The method comprises performing functional testing for each programmable device of a plurality of programmable devices; identifying...
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7616485 |
Semiconductor memory device having faulty cells
In response to a read command received by a system interface unit for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, a controller carries out selective...
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7613960 |
Semiconductor device test apparatus and method
There is provided a semiconductor test apparatus which uses a test processor to apply a test signal to a DUT having a semiconductor device within it to determine whether the memory is acceptable or...
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7613067 |
Soft error robust static random access memory cells
A Static Random Access Memory (SRAM) cell is provided with an improved robustness to radiation induced soft errors. The SRAM cell includes the following elements. First and second storage nodes are...
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7613056 |
Semiconductor memory device
In a semiconductor memory device provided with a redundancy circuit for conducting a repair of defective memory cells, the memory cell defects which are unevenly distributed can be efficiently...
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7610523 |
Method and template for physical-memory allocation for implementing an in-system memory test
An in-system memory testing method includes transparently selecting and “stealing” a portion of memory from the memory system for running memory tests, then running one or more of the numerous...
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7609580 |
Redundancy program circuit and methods thereof
A redundancy program circuit and methods thereof. The redundancy program circuit may include a master fuse circuit with a master fuse outputting an operation enable signal to indicate a master fuse...
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7609579 |
Memory module with failed memory cell repair function and method thereof
A memory module with failed memory cell repair function and method thereof are provided. The memory module comprises a programming interface, a mode register, a control signal generator, a fuse...
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7609569 |
System and method for implementing row redundancy with reduced access time and reduced device area
A system for implementing row redundancy in integrated circuit memory devices includes one or more main subarrays having word line, bit line and memory cell devices, each of the one or more main...
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7607055 |
Semiconductor memory device and method of testing the same
A semiconductor memory device includes at least one first built in self test (BIST) circuit configured to generate test pattern data, and at least one second BIST circuit configured to receive the...
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7606102 |
Memory address repair without enable fuses
A memory chip design methodology is disclosed wherein fuse banks on the memory chip may be implemented without enable fuses. A fuse bank may be enabled by using one or more least significant bits...
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7606092 |
Testing for SRAM memory data retention
A method of testing a memory cell includes generating a logic low signal, generating a logic high signal, reducing the logic high signal to a level corresponding to the logic low signal plus an...
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7606090 |
Redundancy program circuit and methods thereof
A redundancy program circuit and methods thereof. The redundancy program circuit may include a master fuse circuit with a master fuse outputting an operation enable signal to indicate a master fuse...
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7603595 |
Memory test circuit and method
A memory test circuit according to an embodiment of the invention executes a test on a memory in accordance with a pattern mode signal designating a sub-test pattern included in a test pattern and...
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7603516 |
Disk controller providing for the auto-transfer of host-requested-data from a cache memory within a disk memory system
A disk-controller ( 110 ) that is within a disk memory system ( 100 ) initiates the auto-transfer of host-requested-data from cache memory ( 120 ) without the intervention of a microprocessor ( 130...
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7602661 |
Semiconductor memory apparatus and method of controlling the same
A semiconductor memory apparatus configured to have general cells and redundant cells for repairing defective cells among the general cells includes; repair sets configured to determine whether...
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7602660 |
Redundancy circuit semiconductor memory device
A redundancy circuit in a semiconductor memory device comprises a fuse set controller configured to output a redundancy enable signal enabled according to applied address signals; a redundant...
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7602659 |
Memory device having shared fail-repairing circuit capable of repairing row or column fails in memory cell arrays of memory banks
A memory device sharing a fail-repairing part is disclosed. The memory device has a plurality of banks that share a fuse and control unit for repairing a row fail or column fail in memory cell...
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7602642 |
Nonvolatile memory system and associated programming methods
A nonvolatile memory system includes a host system, a memory controller, and a flash memory chip including multi-level flash memory cells. The memory controller includes a backup memory adapted to...
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7602638 |
Semiconductor memory device
A semiconductor memory device is provided which can achieve high performance, such as an improvement in reliability, an improvement in yield, and the like, without increasing the chip area. The...
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7599235 |
Memory correction system and method
An error correction system and method operable to identify and correct a memory module disposed within a computer memory system. In one embodiment, the memory system comprises a first memory module...
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7599205 |
Methods and apparatus of stacking DRAMs
Large capacity memory systems are constructed using stacked memory integrated circuits or chips. The stacked memory chips are constructed in such a way that eliminates problems such as signal...
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7596738 |
Method and apparatus for classifying memory errors
One embodiment of the present invention provides a system that determines the cause of a correctable memory error. First, the system detects a correctable error during an access to a memory...
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7593278 |
Memory element with thermoelectric pulse
A memory element comprises an addressable memory cell. A thermoelectric device couples to the memory cell. Electrical conductors provide a current pulse to the thermoelectric device. The current...
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7593274 |
Semiconductor integrated circuit and relief method and test method of the same
A semiconductor integrated circuit is disclosed, which includes a plurality of memory circuits in which defective columns are relievable, mounted on one chip, each of the memory circuits having a...
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7590015 |
Integrated circuit device and electronic instrument
An integrated circuit device includes a data driver block, a memory block, an information storage block in which an address of a defective cell of the memory block is programmed and stored as a...
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7590001 |
Flash memory with optimized write sector spares
In certain exemplary embodiments, a memory device with optimized write sectors has a plurality P of memory write sectors and N memory spare sectors Cumulatively, the memory write sectors correspond...
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7587645 |
Input circuit of semiconductor memory device and test system having the same
An input circuit of a semiconductor memory device includes a data input circuit and a data pattern setting circuit. The data input circuit receives first data, and generates second data by...
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7586779 |
Controller apparatus for utilizing downgrade memory and method for operating the same
A controller apparatus for utilizing downgrade memory and method for operating the same are proposed. The controller apparatus uses address assignment to access the downgrade memory, which is...
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7583532 |
Charge-trapping memory device and methods for its manufacturing and operation
A method for leveling bit errors in a charge-trapping memory device is included. The memory device has a first and a second sector of memory cells. The first sector is validated by counting a...
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7580320 |
Multi-port memory device
There is provided a column repair technology of a semiconductor memory device. The semiconductor memory device includes: a normal bus connection part for transmitting/receiving data between global...
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7577783 |
Portable data storage device and method of dynamic memory management therefor
A portable data storage device includes a first storage unit having a data storing zone and a reserved zone for bad blocks in the first storage unit, and a second storage unit having a look-up...
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7573763 |
Redundancy circuit
A redundancy circuit can include a first fuse set that is configured to receive an address signal and an initializing signal activated when power is up, and to output a first redundancy signal, the...
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7573762 |
One time programmable element system in an integrated circuit
A system with a repairable memory array having redundant memory cells to replace one or more defective memory cells that are detected after fabrication. The system also includes non memory array...
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7573761 |
Integrated electrical module with regular and redundant elements
An integrated electrical module has a set of regular elements and a set of redundant elements, the elements being split over at least two blocks which are individually selectable by an input...
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7573751 |
Flash memory device having single page buffer structure
A flash memory device includes memory cells, a common node, a sense node connected to a selected bit line, a first register connected to the common node, a second register connected to the common...
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7570536 |
Column redundancy circuit
A column redundancy circuit is disclosed. The column redundancy circuit includes a first control signal generator configured to receive a refresh flag signal having an enable width larger than that...
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7570526 |
Memory device and method of repairing the same
A memory device includes a main memory cell having a plurality of first memory cells for storing data, wherein a special block for storing a column address corresponding to a first memory cell...
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7568960 |
Capacitive signal connector
The present disclosure is directed to connectors and methods for passing signals through capacitive coupling and electron tunneling. The connectors according to the present disclosure can include...
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7567482 |
Block redundancy implementation in heirarchical ram's
The present invention relates to a system and method for providing redundancy in a hierarchically memory, by replacing small blocks in such memory. The present invention provides such redundancy...
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7567466 |
Non-volatile memory with redundancy data buffered in remote buffer circuits
A memory has defective locations in its user portion replaceable by redundant locations in a redundant portion. Data latches in column circuits of user and redundant portions allow data sensed from...
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7566011 |
Semiconductor device
A semiconductor device which may be used as an ID chip and data may be rewritten only one time. In addition, a semiconductor device may be used as an ID chip and data may be written except when...
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7562269 |
Semiconductor storage device
A testing device for a semiconductor storage device which suppresses the increase in the circuit size, provides for facilitated accommodation to a test with frequent changes in the test pattern,...
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7561486 |
Flash memory devices with flash fuse cell arrays
A flash memory device includes a flash cell array, a first flash fuse cell fusing circuit, a second flash fuse cell fusing circuit, a third flash fuse cell fusing circuit and a plurality of fuse...
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7561482 |
Defective block isolation in a non-volatile memory system
A method and apparatus provide an improved identification and isolation of defective blocks in non-volatile memory devices having a plurality of user accessible blocks of non-volatile storage...
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7558096 |
Stacked memory
A stacked memory is configured such that a ratio between data and ECC bits, a ratio between quantities of data layers and ECC layers, and a ratio between quantities of data activated mats and ECC...
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7554857 |
Data output multiplexer
A data output multiplexer for multiplexing and transferring data of a data input/output (I/O) line includes a first latch unit coupled to the data I/O line to latch the data of the data I/O line, a...
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7554353 |
Method of controlling on-die termination of memory devices sharing signal lines
A method of controlling On-Die Termination (ODT) resistors of memory devices sharing signal lines is provided. The ODT controlling method comprises setting an ODT control enable signal of each of...
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7552378 |
Semiconductor device improving error correction processing rate
In an exclusive OR circuit (XOR gate) constituting an ECC circuit, the drivability of P channel MOS transistors is set larger than the drivability of N channel MOS transistors. Accordingly, the...
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7551506 |
Semiconductor apparatus, semiconductor storage apparatus, control signal generation method, and replacing method
A semiconductor apparatus according to the present invention includes a plurality of electric fuses that can be disconnected electrically, a selection circuit selecting the plurality of electric...
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