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8358545 Semiconductor memory  
According to one embodiment, a semiconductor memory includes a memory cell array including a plurality of memory cells, a sense amplifier circuit holding a verification result for the memory cells...
8358548 Methods for efficiently repairing embedded dynamic random-access memory having marginally failing cells  
A test system and a method for efficiently repairing marginally failing memory cells in an embedded dynamic random access memory on an integrated circuit identify marginally failing cells in the...
8351285 Systems, memories, and methods for repair in open digit memory architectures  
Memories, systems, and methods for repairing are provided. A memory with extra digit lines in end arrays with an open digit architecture, which can use the extra digit lines to form repair cells....
8351286 Test method for screening manufacturing defects in a memory array  
A method of screening manufacturing defects at a memory array may include programming a background pattern of physically inverse data along conductive lines extending in a first direction. The...
8345495 Test circuit, nonvolatile semiconductor memory appratus using the same, and test method  
A test circuit of a nonvolatile semiconductor memory apparatus includes a first switching unit, a second switching unit, and a third switching unit. The first switching unit is configured to...
8345494 Semiconductor memory device  
A semiconductor memory device includes a plurality of memory cell mats each comprising a plurality of normal memory cell arrays; and a redundancy memory cell array configured to replace a...
8345493 Semiconductor memory device  
In a semiconductor memory device which performs a repair method of replacing a repair target word line and one adjacent word line at the same time by a repair operation through an efficient...
8345501 Semiconductor memory device correcting fuse data and method of operating the same  
A semiconductor memory device and method of operating same are described. The semiconductor memory device includes a first anti-fuse array having a plurality of first anti-fuse elements that store...
8347154 Use of hashing function to distinguish random and repeat errors in a memory system  
One embodiment provides an error detection method wherein single-bit errors in a memory module are detected and identified as being a random error or a repeat error. Each identified random error...
8339832 Write-once nonvolatile memory with redundancy capability  
A write-once memory can be written only once to each memory cell; therefore, a defective bit cannot be detected by an actual inspection of writing. Accordingly, as described above, the measures,...
8339154 Built-in line test method  
A method for testing a line including an input/output pin of a programmable logic circuit, said line including at least one individual line extending from the input/output pin to a peripheral...
8339880 Circuit for controlling redundancy in semiconductor memory apparatus  
Disclosed are a circuit and a method for controlling redundancy in a semiconductor memory apparatus. The circuit includes a peripheral circuit redundancy control block and a memory bank redundancy...
8339853 Nonvolatile semiconductor storage device, nonvolatile semiconductor storage system and method of managing of defective column in nonvolatile semiconductor storage system  
A nonvolatile semiconductor storage device is disclosed, which includes a memory cell array in which nonvolatile memory cells are arranged, a first data holding circuit which temporarily holds a...
8339889 Semiconductor memory device  
A semiconductor memory device includes a memory core; a charge pump circuit providing a high voltage to the memory core; and a charge pump control circuit operating the charge pump circuit by a...
8339830 Nonvolatile semiconductor storage  
According to one embodiment, a memory cell is configured using a field effect transistor and includes n anti-fuse elements, one ends of which are connected in common. A program voltage selection...
8339868 Semiconductor device and write control method for semiconductor device  
To include a memory cell array that stores therein data in a reversible manner, an antifuse circuit that stores therein data in a nonvolatile manner, a sense amplifier array that temporarily holds...
8335118 Method of operating a flash memory device  
A flash memory device is disclosed. The flash memory device includes a memory cell array configured to have memory cells for storing data, and store initial data in a part of the memory cells, a...
8332725 Reprogramming non volatile memory portions  
A system and a method for reprogramming a non volatile memory (NVM) portion, the method includes: receiving an initial content of an NVM portion; wherein the initial content differs from an erase...
8331174 Semiconductor memory device and method for operating the same  
A semiconductor memory device includes: a repair address generation unit configured to generate a repair address signal in response to a first address signal; a line choice address generation unit...
8331122 Semiconductor device and information processing system including the same  
A semiconductor device includes plural core chips and an interface chip that controls the plural core chips. Each of the plural core chips includes a layer address generating circuit that...
8331151 Semiconductor memory including control unit responsive to erase command to determine selection of redundant memory block  
A semiconductor memory device includes a memory region including memory cells configured to store data, a redundant region including memory cells configured to store data, and a control unit. The...
8331186 Fuse programming schemes for robust yield  
A program circuit generates first and second currents to program the fuse. The second current is higher than the first current. A control circuit controls generating the first and second currents...
8325546 Method and system for processing a repair address in a semiconductor memory apparatus  
A semiconductor memory apparatus includes a memory device having a first plane and a second plane and a repair address latch unit configured to latch a plurality of repair addresses outputted from...
8325548 Semiconductor device and semiconductor device test method for identifying a defective portion  
A semiconductor device includes a first memory including a first memory cell and a first redundant memory cell; a first test circuit configured to test the first memory and output first defect...
8325547 Test apparatus and repair analysis method  
A test apparatus that tests a memory under test, comprising an address fail memory that stores address fail data for each address; a block fail memory that stores block fail data for each block; a...
8324958 Redundancy circuits  
In one embodiment, a redundancy circuit may include a comparison unit configured to record a first repair address through fuse cutting, compare a comparison address with the first repair address,...
8324709 Semiconductor device  
A semiconductor device has an electrical fuse formed on a substrate, having a first interconnect, a second interconnect respectively formed in different layers, and a via provided in a layer...
8321623 Ad hoc flash memory reference cells  
In a nonvolatile memory, that includes cells organized in a plurality of bit lines and a plurality of word lines, user data are stored in respective portions of each of two of the word lines....
8320206 Stacked device remapping and repair  
Various embodiments include apparatus, systems, and methods having multiple dice arranged in a stack in which a defective cell may be replaced by a spare cell on the same die or a different die....
8315117 Integrated circuit memory having assisted access and method therefor  
A memory and method for access the memory are provided. A first test is used to test memory elements to determine a lowest power supply voltage at which all the memory elements will operate to...
8315116 Repair circuit and repair method of semiconductor memory apparatus  
A repair circuit of a semiconductor memory apparatus includes a repair address detection circuit that determines the occurrence of a failure in a memory block based on a plurality of test data...
8315115 Method for testing a main memory  
A method for testing a primary memory of control and regulation electronics of a frequency converter is described. The primary memory includes (i) at least one matrix of memory cells, (ii) means...
8310888 Repair fuse device  
A repair fuse device is provided. The repair fuse device remarkably reduces the number of the enable fuse cuttings by making initial states of all repair fuse sets to a repair state, cutting an...
8307261 Non-volatile memory management method  
A management method for a non-volatile memory comprises the steps of providing the non-volatile memory with at least one block having a plurality of pages to store user data and parity data;...
8305822 Fuse circuit and semiconductor memory device including the same  
The fuse circuit includes a first program unit, a second program unit and a sensing circuit. The first and second program units are programmed simultaneously. The first program unit is programmed...
8296611 Test circuit for input/output array and method and storage device thereof  
The invention provides a test circuit for n input/output arrays. Each of the n input/output arrays has M pairs of input/output. The test circuit includes M write drivers and M comparing circuits....
8295108 Architecture, system and method for compressing repair data in an integrated circuit (IC) design  
Architecture, system and method for providing compression of repair data in an IC design having a plurality of memory instances. In one embodiment, the repair data storage method includes...
8295109 Replacing defective columns of memory cells in response to external addresses  
Controllers and memory devices are provided. In an embodiment, a controller is configured to address a non-defective column of memory cells of a memory device in place of a defective column of...
8291152 Method for operating non-volatile memory and data storage system using the same  
A method for operating a non-volatile memory is provided. The non-volatile memory includes a plurality of physical blocks having a plurality of data blocks and spare blocks. An index is obtained...
8289792 Memory test circuit, semiconductor integrated circuit and memory test method  
A memory test circuit tests a memory including an actual array portion and a redundancy portion. The memory test circuit includes: an input data selector outputting first test data excluding data...
8289790 Memory repair systems and methods for a memory having redundant memory  
Memories, memory repair logic, and methods for repairing a memory having redundant memory are disclosed. One such memory includes programmable elements associated with respective redundant memory...
8279696 Semiconductor device  
There is provided a technique for ensuring both an SNM and a write margin simultaneously in a semiconductor device having static memory cells. A semiconductor device has a plurality of static...
8279655 Non-volatile semiconductor memory device and method of controlling non-volatile semiconductor memory device  
According to an embodiment, there are provided a non-volatile semiconductor memory device includes: a memory cell array; a control circuit performing a series of operations to each memory cell and...
8279990 Transmitting/receiving system and method of processing data in the transmitting/receiving system  
A transmitting/receiving system and a data processing method of the same are disclosed herein. The receiving system may include a receiving unit, a first processing unit, and a second processing...
8279668 Apparatus and method of memory programming  
A memory programming apparatuses and/or methods are provided. The memory programming apparatus may include a data storage unit, a first counting unit, an index storage unit and/or a programming...
8270238 Integrated circuits and methods to compensate for defective non-volatile embedded memory in one or more layers of vertically stacked non-volatile embedded memory  
Embodiments of the invention relate generally to data storage and computer memory, and more particularly, to systems, integrated circuits and methods to compensate for defective memory in third...
8270237 Semiconductor device, relief-address-information writing device, and relief-address-information writing method  
To provided a relief-address generating circuit that generates relief address information based on plural data bits supplied in time sequence via a first terminal from outside and a programming...
8270240 Current leakage reduction  
An OTP memory array includes a bit line coupled to a plurality of memory banks. Each memory bank includes a plurality of memory cells, a footer, and a bias device, and is associated with a current...
8266484 Circuits, architectures, apparatuses, systems, methods, algorithms, software and firmware for using reserved cells to indicate defect positions  
A system including a plurality of data storage cells, where each of the plurality of data storage cells is configured to store a plurality of data bits, and a plurality of reserved cells...
8264902 Memory control method and memory control device  
A memory control method that carries out first-in first-out access control for a memory having a plurality of storage areas, including: selecting, as write positions, an address of a storage area...