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8134880 Semiconductor integrated circuit  
A semiconductor integrated circuit has a plurality of memory devices each comprising a memory cell array which includes a plurality of memory cells to store data, a spare part which includes a...
8134879 Semiconductor memory device having redundancy circuit for repairing defective unit cell, and method for repairing defective unit cell  
A semiconductor memory device includes banks of unit cells, wherein two or more adjacent banks of the banks share a redundancy circuit configured to perform a defect repair operation when an...
8134872 Apparatus and methods for programming multilevel-cell NAND memory devices  
Methods and apparatus are provided. A first data value is read from a first memory cell and is stored. An attempt is made to add a second data value to the first memory cell. If the attempt to add...
8130557 Memory system and method of writing into nonvolatile semiconductor memory  
A memory system includes a nonvolatile semiconductor memory which includes a first original block composed of n (n being natural number) write unit areas and a first subblock composed of a...
8130575 Semiconductor device  
A highly reliable large capacity phase change memory module is realized. A semiconductor device according to the present invention includes a memory array having a structure in which a storage...
8130572 Low power memory array column redundancy mechanism  
A low power memory array column redundancy mechanism includes a memory unit having a memory array and a multiplexer unit. The memory array includes a plurality of columns, which includes a...
8125843 Semiconductor memory device and method for testing the same  
A semiconductor memory device includes a memory cell array, a data input/output terminal, a data input/output circuit, and a test circuit. The data input/output circuit is provided between the...
8120987 Structure and method for decoding read data-bus with column-steering redundancy  
A random access memory circuit enabling a decodable sense amplifier array for power saving with column steering redundancy. A first decoder receives an input address and accesses at least one...
8120957 Nonvolatile semiconductor storage device, nonvolatile semiconductor storage system and method of managing of defective column in nonvolatile semiconductor storage system  
A nonvolatile semiconductor storage device is disclosed, which includes a memory cell array in which nonvolatile memory cells are arranged, a first data holding circuit which temporarily holds a...
8116156 Semiconductor memory device  
There are provided a row predecoder that predocodes an address irrespective of whether the address to which access is requested is a defective address, a row main decoder that controls a sub-word...
8117510 Circuits, architectures, apparatuses, systems, methods, algorithms, software and firmware for using reserved cells to indicate defect positions  
A circuit including a memory and an error correction code circuit. The memory including (i) a plurality of data storage cells and (ii) at least one reserved cell configured to store status...
8116163 Semiconductor memory device  
The present invention provides a semiconductor memory device that includes: a fuse circuit having multiple fuse elements; and a fuse selection circuit connected to an internal address signal line...
8111567 Semiconductor device  
An object is to provide a semiconductor device having a memory which can efficiently improve a yield by employing a structure which facilitates the use of a spare memory cell. The semiconductor...
8111532 Method and apparatus for CAM with redundancy  
Aspects of the disclosure provide a CAM module that can be used independent of a defective entry line. The CAM module can include at least a CAM array having at least X CAM entry lines, and an...
8112681 Method and apparatus for handling fuse data for repairing faulty elements within an IC  
The application discloses an integrated circuit comprising: circuitry; a fusebox for storing an array of data identifying faulty elements within said circuitry; at least one fusebox controller for...
8103546 Advertising content delivery  
Programming media and advertising media may be presented in a manner that approximates or equals a target ratio. In one implementation, a total temporal length of one or more programming media...
8098536 Self-repair integrated circuit and repair method  
A method for repairing degraded field effect transistors includes forward biasing PN junctions of one of a source and a drain of a field effect transistor (FET), and a body of the FET. Charge is...
8095853 Digital memory with fine grain write operation  
Methods, systems, and apparatus for operating digital memory including determining, by a controller, a bit to be written to the digital memory and writing, by the controller, the bit. The bit may...
8086914 Storing data to multi-chip low-latency random read memory device using non-aligned striping  
Described herein are method and apparatus for storing data to a low-latency random read memory (LLRRM) device using non-aligned data striping, the LLRRM device being implemented on a storage...
8085592 Charge-trap flash memory device with reduced erasure stress and related programming and erasing methods thereof  
Operation methods of charge-trap flash memory devices having an unused memory cell for data storage and a normal memory cell used for data storage are discussed. The operation method may include...
8081511 Flash memory device with redundant columns  
Apparatus and methods are disclosed, such as those involving a flash memory device. One such apparatus includes a memory block including a plurality of columns. Each of the columns includes a bit...
8081529 Circuit and method for testing multi-device systems  
A method and system for high speed testing of memories in a multi-device system, where individual devices of the multi-device system are arranged in a serial interconnected configuration. High...
8081528 Integrated circuit and method for testing the circuit  
An integrated circuit includes a memory; a memory test circuit that tests the memory; and an input/output port, wherein the memory test circuit includes a latch circuit that outputs output of the...
8077532 Small unit internal verify read in a memory device  
Methods for small unit internal verify read operation and a memory device are disclosed. In one such method, expected data is programmed into a grouping of columns of memory cells (e.g., memory...
8077531 Semiconductor integrated circuit including column redundancy fuse block  
A semiconductor integrated circuit includes a semiconductor chip having an edge area and a bank area located an inner portion of the edge area, and a column redundancy fuse block disposed in the...
8072827 Semiconductor storage device having redundancy area  
A semiconductor storage device is provided with: a memory cell array which includes a normal area and a redundancy area which replaces a defective memory cell in the normal area; a normal area...
8072808 Nonvolatile semiconductor memory device  
A memory cell array including at least one memory cell, an address storage section containing address information, an address judging circuit for judging whether an input address matches the...
8074130 Test apparatus  
A test apparatus includes a test section that executes testing of each cell of the memory under test, a fail information storage section that stores fail information in a fail memory; a counting...
8069383 ***WITHDRAWN PATENT AS PER THE LATEST USPTO WITHDRAWN LIST***
Apparatus, system, and method for bad block remapping
 
An apparatus, system, and method are disclosed for bad block remapping. A bad block identifier module identifies one or more data blocks on a solid-state storage element as bad blocks. A log...
8068375 Semiconductor device and method of refreshing the same  
A semiconductor device according to the present invention has an address scrambling circuit for performing address scrambling operation of an address and a redundancy judging circuit for judging...
8068363 Flash memory apparatus and read operation control method therefor  
A flash memory apparatus of an embodiment is configured to include a flash memory including a plurality of blocks and a read operation control circuit determining whether to replace a block in...
8068113 Display control semiconductor integrated circuit  
The present invention provides a display control semiconductor integrated circuit having therein a RAM, capable of repairing a defective bit included in the RAM and improving the yield without...
8068380 Block repair scheme  
Systems, memory arrays and methods (e.g., methods of block repair) are provided. One such system includes a memory array including a memory bank including a plurality of sections, wherein each of...
8064257 Semiconductor memory device having faulty cells  
In response to a read command received by a system interface unit for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, a controller carries out selective...
8064258 Method apparatus, and system providing adjustable memory page configuration  
A method, apparatus and system providing a memory device having an array of cells which may be selectively designated for either error correction code use or redundancy cell use.
8065589 Semiconductor memory device  
A semiconductor memory device includes a memory cell array from which all bits of a data signal having a first number of the bits composed of a main data signal and an error detection/correction...
8064278 Protection register for a non-volatile memory  
A non-volatile memory including a plurality of memory cells configured to store data and a plurality of redundant memory cells configured to be used for functionally replacing defective memory...
8065573 Method and apparatus for tracking, reporting and correcting single-bit memory errors  
Various embodiments include an apparatus comprising a memory device including a plurality of addressable memory locations, and a memory manager coupled to the memory device, the memory manager...
8059477 Redundancy circuit of semiconductor memory  
A redundancy circuit of a semiconductor memory apparatus includes an enable signal generation unit configured to have a plurality of enable fuses corresponding to a first mat grouping information...
8054704 Semiconductor memory device having a redundancy memory cell array  
A semiconductor memory device includes a plurality of memory cell mats each comprising a plurality of normal memory cell arrays; and a redundancy memory cell array configured to replace a...
8055957 Semiconductor integrated circuit device having fail-safe mode and memory control method  
An integrated circuit device contains a flash memory, a flash control unit for controlling the rewriting and reading on the flash memory, and a processor unit. The processor unit includes a normal...
8054678 Stuck-at defect condition repair for a non-volatile memory cell  
A method and apparatus for repairing a stuck-at defect condition in a non-volatile memory cell, such as a spin-torque transfer random access memory (STRAM). In some embodiments, a resistive sense...
8055969 Multi-strobe circuit  
A multi-strobe circuit that latches a signal to be tested, an evaluation target, at each edge timing of a multi-strobe signal having a plurality of edges. An oscillator oscillates at a...
8051342 Semiconductor memory device  
A semiconductor memory device including: a memory cell array including a plurality of word lines, a plurality of bit lines, and memory cells arranged in portions where the plurality of word lines...
8050122 Fuse apparatus for controlling built-in self stress and control method thereof  
A fuse apparatus for controlling a built-in self stress unit includes a built-in self stress configured to repeatedly generate any stress test pattern in a test mode, and generate a one-cycle end...
8050121 Semiconductor memory, system, operating method of semiconductor memory, and manufacturing method of semiconductor memory  
A plurality of memory blocks includes real memory cells and redundancy memory cells, are accessed independently during a normal operation mode, and are accessed simultaneously during a test mode...
8040744 Spare block management of non-volatile memories  
Techniques for the management of spare blocks in re-programmable non-volatile memory system, such as a flash EEPROM system, are presented. In one set of techniques, for a memory partitioned into...
8040745 Stacked memory and fuse chip  
A stacked memory comprises one or more memory core chips and a fuse chip. Each of the memory core chips has a memory cell array including spare memory cells for replacing defective memory cells....
8041916 Data storage device and method of operating the same  
A data storage device and a method of operating the same include firmware recognizing that the data storage device has a smaller than normal capacity or includes a routine in the firmware when the...
8036054 Semiconductor memory device with improved sensing margin  
A semiconductor memory device includes a signal generating unit for generating first and second enable signals in response to a power-up signal, a first sub-word line signal driving unit for...