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9026833 Semiconductor device and method for fetching data  
In order to reduce occurrence of a fetching error of a digital signal, caused by a power-source noise, there is provided a semiconductor device provided with a switching circuit for executing a...
9003148 Microcomputer and method for controlling memory access  
A microcomputer includes a CPU, a protection information storage configured to store memory protection information specifying an access permission or a prohibited state to a memory space by a...
8995211 Program condition dependent bit line charge rate  
Methods and devices for charging unselected bit lines are disclosed. The rate at which inhibited (or unselected) bit lines are charged may depend on a program condition. The program condition may...
8988943 Semiconductor memory device and operating method thereof  
A semiconductor memory device and a method of operating a semiconductor memory device includes connecting selected even bit lines to selected even cell strings, programming memory cells in the...
8982620 Non-volatile memory device and method of operating  
A method of operating a non-volatile memory includes; during power-on, reading control information from an information block and lock information from an additional information block, then upon...
8976585 Memory module for simultaneously providing at least one secure and at least one insecure memory area  
A memory module has at least one secure and at least one insecure memory area, separate write/read electronic units for each of the memory areas and at least one shared analog circuit part such as...
8976590 Semiconductor memory device  
A semiconductor memory device includes a memory block as a code storage memory area which has a large memory capacity and in which the number of bits to be written at once is large, and a memory...
8964489 Semiconductor memory device capable of optimizing an operation time of a boosting circuit during a writing period  
When writing into an antifuse memory element finishes, a value of resistance of the memory element rapidly decreases; accordingly, an output voltage of a boosting circuit which produces a writing...
8913447 Method and apparatus for memory command input and control  
Memories containing command decoder, chip enable, and signal truncation circuits are disclosed. One such command decoder circuit may include command decoder logic configured to receive command...
8908441 Double verify method in multi-pass programming to suppress read noise  
Memory cells which have read noise are identified during a programming pass and an amount of programming is increased for noisy memory cells compared to non-noisy cells. The read noise is...
8908409 Stable SRAM cell  
SRAM cells and SRAM cell arrays are described. In one embodiment, an SRAM cell includes a first inverter and a second inverter cross-coupled with the first inverter to form a first data storage...
8908456 Semiconductor memory device and operating method thereof  
An operating method of a semiconductor memory device includes precharging a channel region of a program-inhibited cell of first memory cells coupled to a first word line, selected from a first one...
8908453 Data retention kill function  
Various data protection techniques are provided. In one embodiment, a memory device is provided. The memory device may initiate a security measure upon occurrence of one or more triggering events....
8902668 Double verify method with soft programming to suppress read noise  
Memory cells which have read noise are identified during a programming pass and an amount of programming is increased for noisy memory cells compared to non-noisy cells. The read noise is...
8902659 Shared-bit-line bit line setup scheme  
Methods for operating a non-volatile storage system utilizing a shared-bit-line NAND architecture are described. A shared-bit-line NAND architecture includes one or more pairs of NAND strings,...
8873307 Semiconductor device  
A semiconductor device includes a sense amplifier, transistors selectively establishing electrical connection between the sense amplifier and a data bus, depending on address; a write amplifier...
8867267 Memory devices, memory device constructions, constructions, memory device forming methods, current conducting devices, and memory cell programming methods  
Some embodiments include memory devices having a wordline, a bitline, a memory element selectively configurable in one of three or more different resistive states, and a diode configured to allow...
8848477 Physical unclonable function with improved start-up behavior  
An electric physical unclonable function (PUF) (100) is provided comprising a semiconductor memory element (110) connectable to a PUF control means for reading content from the memory element and...
8787059 Cascaded content addressable memory array having multiple row segment activation  
A content addressable memory (CAM) device has an array including a plurality of CAM rows that are partitioned into row segments, wherein a respective row includes a first row segment including a...
8782350 Circuit providing load isolation and noise reduction  
Certain embodiments described herein include a memory module having a printed circuit board including at least one connector configured to be operatively coupled to a memory controller of a...
8767444 Radiation-hardened memory element with multiple delay elements  
A radiation hardened memory element includes at least two delay elements for maintaining radiation hardness. In an example, the memory element is an SRAM cell. Both delays are coupled together in...
8743649 Semiconductor memory, system, and method of operating semiconductor memory  
A memory has memory cells in a matrix; a first selection unit selecting any of first signal lines in the memory cells, in response to an access request; a second selection unit selecting any of...
8681558 Parallel bitline nonvolatile memory employing channel-based processing technology  
Providing for a new combination of non-volatile memory architecture and memory processing technology is described herein. By way of example, disclosed is a parallel bitline semiconductor...
8670275 Memory with sub-blocks  
The apparatuses and methods described herein may comprise a memory array formed on a semiconductor substrate and including a plurality of cells associated with a plurality of word lines. The...
8638624 Architecture and method for memory programming  
Methods of programming a memory, memory devices, and systems are disclosed, for example. In one such method, each data line of a memory to be programmed is biased differently depending upon...
8638606 Substrate bias during program of non-volatile storage  
A programming technique which reduces program disturb in a non-volatile storage system is disclosed. A positive voltage may be applied to a substrate (e.g., p-well) during programming. Biasing the...
8619474 Data line management in a memory device  
Memory devices and methods are disclosed, such as devices configured to apply a first program inhibit bias to data lines during a first portion of a program operation and to apply a second program...
8576629 Operating method of nonvolatile memory device  
Disclosed is an operating method of a nonvolatile memory device, which includes programming the first selection transistors of the plurality of cell strings and programming the plurality of memory...
8565035 Data retention kill function  
Various data protection techniques are provided. In one embodiment, a memory device is provided. The memory device may initiate a security measure upon occurrence of one or more triggering events....
8537624 Semiconductor memory device and method of operating the same  
A semiconductor memory device that may perform a second operation during a first operation comprises a command decoder for generating a decoded command signal, a suspend pulse and a resume pulse,...
8493809 Refresh control circuit and semiconductor memory apparatus using the same  
A refresh control circuit is capable of activating a plurality of bank selection signals in response to a refresh command signal. Each of the plurality of bank selection signals is assigned to one...
8451680 Method of driving a semiconductor memory device with a sense amplifier controller for maintaining the connection of a previously selected memory cell array  
A semiconductor memory device includes a bit line sense amplifier block array, upper and lower memory cell arrays and a sense amplifier controller. The bit line sense amplifier block array senses...
8437207 Apparatus for measuring data setup/hold time  
An apparatus for measuring data setup/hold time is capable of effectively measuring a setup/hold time of data, and includes a data generating unit for delaying an external clock signal according...
8432756 Collision prevention in a dual port memory  
A dual port memory includes a mechanism for preventing collisions. The memory includes dual port bit cells arranged in rows and columns and each bit cell stores a data bit. The memory also...
8427881 Semiconductor memory device and programming method thereof  
A programming method of a semiconductor memory device includes charging a channel of an inhibit string to a precharge voltage provided to the common source line and boosting the charged channel by...
8395957 Circuit and method for controlling self-refresh operation in semiconductor memory device  
A self-refresh control circuit includes: a code generator configured to generate a code by counting periods of a periodic wave based on a self-refresh signal and reset when a code value of the...
8375172 Preventing fast read before write in static random access memory arrays  
A mechanism is provided for enabling a proper write through during a write-through operation. Responsive to determining the memory access as a write-through operation, first circuitry determines...
8355294 Synchronous data processing system for reliable transfer of data irrespective of propagation delays and process, voltage and temperature (PVT) variations  
A synchronous data processing system includes a memory module to store data and a memory controller coupled to the memory module. The memory controller includes a clock inverter to receive an...
8339857 Nonvolatile semiconductor memory device and operation method thereof  
A nonvolatile semiconductor memory device according to one embodiment includes: a memory cell array; word lines; bit lines; and a control circuit configured to write multi-value data in the memory...
8335117 Memory device with inhibit control sections  
Disclosed herein is a memory device including: first and second wires; memory cells including a variable-resistance storage element having a data storage state making a transition by a change of a...
8325545 Nonvolatile semiconductor memory device  
According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array, threshold voltages of memory cells being set lowest in an erase state and sequentially set...
8312238 Microcomputer and method for controlling memory access  
A microcomputer includes a CPU, a protection information storage configured to store memory protection information specifying an access permission or prohibited state to a memory space by a...
8295101 Semiconductor device  
A semiconductor device includes a sense amplifier, transistors selectively establishing electrical connection between the sense amplifier and a data bus, depending on address; a write amplifier...
8254186 Circuit for verifying the write enable of a one time programmable memory  
A memory system including a one time programmable (OTP) memory is provided. The memory system further includes a write enable verification circuit including an asymmetric inverter stage and a...
8228522 Document data management apparatus to manage document data read and digitized by an image reading apparatus and a technique to improve reliability of various processing using document data  
In a document data management apparatus to manage document data read and digitized by an image reading apparatus, management of the document data is performed in view of the reliability of an...
8223527 Semiconductor device having memory array, method of writing, and systems associated therewith  
In one embodiment, the semiconductor device, includes a non-volatile memory cell array, and a control unit configured to generate a mode signal indicating if a flash mode has been enabled. A write...
8218180 Image forming apparatus and method for inhibiting the transmission of document data  
An image forming apparatus includes an image receiving unit configured to receive image data, a sender identifying unit configured to identify a sender of the received image data, a check unit...
8208323 Method and apparatus for protection of non-volatile memory in presence of out-of-specification operating voltage  
A method and apparatus for protecting non-volatile memory is described. A write command is processed only when an operating voltage is between specified operating limits and when a data pattern...
8155905 Method of extracting a time constant from complex random telegraph signals  
A method and apparatus for extracting a time constant from a time series of values of a signal that varies in accordance with multiple charge carrier trap defects that cause Random Telegraph Noise...
8156280 Data protection for non-volatile semiconductor memory using block protection  
Receiving a request for canceling setting, a control circuit erases data stored in a corresponding block, changes a value of a protection flag, and cancels protection setting. When an overall...