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7609561 |
Disabling faulty flash memory dies
Articles and associated methods and systems relate to disabling defective flash memory dies in a device containing multiple flash memory dies. Packages containing multiple flash memory dies may be...
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7602656 |
Power supply control circuit and controlling method thereof
A power supply control circuit and a control method secure an accurate operation of a GIO in a burst data transmission having a high compression rate. The power supply control circuit of a...
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7580318 |
Address buffer circuit and method for controlling the same
An address buffer circuit for a semiconductor memory device wherein an address buffer is enabled (to output an internal address signal) in response to a first level of a control signal and, but is...
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7577057 |
Circuit and method for generating write data mask signal in synchronous semiconductor memory device
A circuit for generating a write data mask signal in a synchronous semiconductor memory device includes an output unit and a reset control unit. The output unit controls a write data mask operation...
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7573769 |
Enable signal generator counteracting delay variations for producing a constant sense amplifier enable signal and methods thereof
A sense amplifier enable signal generator has two stages. Each stage offsets transistor performance variation in the other stage to produce an enable signal output relatively immune from the...
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7564727 |
Apparatus and method for configurable power management
A method and apparatus to facilitate low-power consumption through a configurable suspend mode of operation of a PLD, the PLD comprising an application logic block coupled to receive configuration...
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7551497 |
Memory circuits preventing false programming
Memory circuits capable of preventing false programming caused by power-up sequence are provided, in which a programmable unit comprises a plurality of programmable elements, a source bus coupled...
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7546424 |
Embedded processor with dual-port SRAM for programmable logic
Methods and apparatus for programmable logic devices including embedded processors having a dual-port SRAMs. A programmable logic integrated circuit includes a programmable logic portion having a...
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7532524 |
Bitline exclusion in verification operation
Methods and apparatuses for disabling a bad bitline for verification operations, and for determining whether a programming operation have failed, include setting a bitline disable latch for a bad...
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7529144 |
Hierarchical semiconductor memory device capable of carrying out a disturb refresh test on a memory array basis
A semiconductor memory device of the present invention provides, in a memory having an hierarchical bit line structure, a test mode which causes all switches for selecting hierarchical bit lines...
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7512761 |
Programmable processor and methods thereof having memory access locking
A programmable processor and methods thereof are provided. The example programmable processor may include a memory lock signal generator outputting a memory lock signal, the memory lock signal...
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7512711 |
Scalable network apparatus for content based switching or validation acceleration
A network apparatus is provided that may include one or more security accelerators. The network apparatus also includes a plurality of network units cascaded together. According to one embodiment,...
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7511988 |
Static noise-immune SRAM cells
A static random access memory (SRAM) cell includes a first load device, a first pull-down transistor, and a switch-box coupled between the first load device and the first pull-down transistor. The...
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7502256 |
Systems and methods for reducing unauthorized data recovery from solid-state storage devices
A memory system comprising one or more memory devices is purged to prevent unauthorized access to data stored therein. A host system passes control of purge operations to the memory system. The...
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7492651 |
Semiconductor memory apparatus
A first input unit, coupled to a repair checking node through a first fuse, is for inverting a logic level of the repair checking node in response to a first address. A second input unit, coupled...
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7492648 |
Reducing leakage current in memory device using bitline isolation
A method for reducing defect leakage current in a semiconductor memory device comprising a plurality of memory banks, each memory bank comprising a plurality of memory arrays and sense amplifier...
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7492632 |
Memory array having a programmable word length, and method of operating same
A memory cell array and device having a memory cell array (i.e., an integrated circuit device, for example, a logic device (such as, a microcontroller or microprocessor) or a memory device (such...
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7486584 |
Semiconductor memory device and refresh control method thereof
A semiconductor memory device has a refresh control circuit for switchingly controlling a first refresh mode in which access to the memory cell array from outside is prohibited while retaining data...
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7486576 |
Methods and devices for preventing data stored in memory from being read out
A dynamic random access memory (DRAM) device, including a DRAM core having memory cells for storing data information, and a read protection unit, prevents data stored in the memory cells before...
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7486535 |
Method and device for programming anti-fuses
A device includes an anti-fuse including a first electrode that can be selectively coupled to a first voltage reference and a second electrode that can be selectively coupled to a second voltage...
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7477554 |
Data retention kill function
A method for operating a memory device is disclosed. In one embodiment, the method includes receiving authorized operating parameters of the memory device and comparing sensed operational...
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7468924 |
Non-volatile memory device capable of reducing threshold voltage distribution
A method for programming a flash memory device which includes a plurality of memory cells arranged in rows and columns. The method includes programming selected memory cells from among the...
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7447086 |
Selective program voltage ramp rates in non-volatile memory
A non-volatile memory system is programmed so as to reduce or avoid program disturb. In accordance with one embodiment, multiple program inhibit schemes are employed for a single non-volatile...
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7440312 |
Memory write timing system
A memory write timing system includes a modified memory bitcell including a storage device and a write/read circuit for writing/reading data to/from the storage device; and an output circuit for...
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7437500 |
Configurable high-speed memory interface subsystem
A core including a write logic IP block, a read logic IP block, a master delay IP block and an address and control IP block. The write logic IP block may be configured to communicate data from a...
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7433260 |
Memory device and print recording material receptacle providing memory device
The operation code decoder 204 having received an access enable signal EN acquires and decodes the command, and sends the decoded command to the read/write controller 206 . In the event that the...
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7430136 |
Purge operations for solid-state storage devices
A storage system that comprises multiple solid-state storage devices includes a command set that enables a host system to initiate one or more types of purge operations. The supported purge...
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7430041 |
Semiconductor storage apparatus
A semiconductor storage apparatus according to one embodiment of the present invention, comprising: memory cells which need refresh operation; and a refresh control circuit which suspends the...
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7428171 |
Non-volatile memory and method with improved sensing
A method for reducing source line bias is accomplished by read/write circuits with features and techniques for multi-pass sensing. When a page of memory cells are being sensed in parallel, each...
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7421534 |
Data protection for non-volatile semiconductor memory using block protection flags
Receiving a request for canceling setting, a control circuit erases data stored in a corresponding block, changes a value of a protection flag, and cancels protection setting. When an overall...
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7417918 |
Method and apparatus for configuring the operating speed of a programmable logic device through a self-timed reference circuit
Method and apparatus for configuring a programmable logic device to operate at a plurality of clock frequencies comprising configurable programmable self-timed delay circuits and associated...
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7414899 |
Method and apparatus for early write termination in a semiconductor memory
A synchronous DRAM (SDRAM) terminates a write operation in response to detecting deactivation of a data strobe signal applied to it during the write operation. In one example, the SDRAM comprises a...
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7408823 |
Semiconductor device and method thereof
A semiconductor device and method thereof. The semiconductor device may include a protection unit receiving an input signal and outputting a switching control signal based on the received input...
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7397727 |
Write burst stop function in low power DDR sDRAM
A write burst stop command function is provided for a semiconductor memory device, and in particular for a memory device having a write latency, such as is common in a low power double data rate...
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7391662 |
Semiconductor memory device with redundancy circuit
A semiconductor device has a memory cell, decoders, a redundancy circuit and a mode setting circuit. The memory cell array has word lines including a redundant word line, bit lines and memory...
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7379356 |
Memory, integrated circuit and methods for adjusting a sense amp enable signal used therewith
A memory includes at least one memory segment that includes an array of memory cells arranged in a plurality of columns, each of the plurality of columns having a corresponding bitline pair. An...
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7379354 |
Methods and apparatus to provide voltage control for SRAM write assist circuits
Methods and apparatus to control voltage output of a write assist circuit are disclosed. An example method includes regulating pull down voltage from a write assist circuit having a write assist...
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7376010 |
Nonvolatile semiconductor memory device having protection function for each memory block
A nonvolatile semiconductor memory device includes a memory cell array constituted by a plurality of memory blocks, an interface, a write circuit, and a read circuit. A protect flag is written in...
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7372759 |
Power supply control circuit and controlling method thereof
The present invention provides a power supply control circuit and a control method thereof, capable of securing an accurate operation of a GIO in a burst data transmission having a high compression...
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7366860 |
Storage device configured to sequentially input a command
A storage device is capable of sequentially inputting a command, which includes address information and attached information, from an information processor through an input/output unit. The storage...
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7366043 |
Current reduction circuit of semiconductor device
A current reduction circuit of a semiconductor device is disclosed which includes an enabling signal generator which outputs a predetermined enabling signal in association with a cell block in...
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7360049 |
Non-volatile semiconductor memory device having a password protection function
In a nonvolatile semiconductor memory device according to the present invention, a password protection function is enabled or disabled based on a first specified value M and a second state...
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7359251 |
Non-volatile semiconductor memory device, erase method for same, and test method for same
A non-volatile semiconductor memory device includes a memory cell array and an operation control circuit. The memory cell array includes a plurality of non-volatile memory cells that are...
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7345930 |
Write circuit of memory device
A write circuit of a semiconductor memory device includes a global data input/output (I/O) line; an amplifying block for receiving and amplifying write data and transmitting the amplified write...
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7339851 |
Word line driving circuit of semiconductor memory device
Disclosed herein is a word line driving circuit in which sub-word lines are prevented from floating by using a sub-word line driver having two transistors. A plurality of sub-word line drivers is...
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7333386 |
Extraction of a binary code based on physical parameters of an integrated circuit through programming resistors
An integrated cell for extracting a binary value based on a value difference between two resistors values, including connection circuitry for a binary reading of the sign of the difference between...
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7330391 |
Memory having directed auto-refresh
A memory includes at least two memory banks, each memory bank including an array of memory cells including rows and columns. The memory includes a directed auto-refresh memory bank selection...
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7315479 |
Redundant memory incorporating serially-connected relief information storage
A relief processing section which performs a relief process with respect to a redundant memory comprises a plurality of defect relief sections each having shift register circuits (relief...
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7310277 |
Non-volatile semiconductor storage device with specific command enable/disable control signal
The non-volatile semiconductor storage device 101 includes the specific command Enable/Disable signal lines 120 connected to the command decoder 108 . The specific command Enable/Disable...
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7295478 |
Selective application of program inhibit schemes in non-volatile memory
A non-volatile memory system is programmed so as to reduce or avoid program disturb. In accordance with one embodiment, multiple program inhibit schemes are employed for a single non-volatile...
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