Matches 301 - 350 out of 734 < 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >
Match Document Document Title
5802558 Method and apparatus for upgrading reprogrammable memory contents in a PCMCIA card  
An apparatus and a method for upgrading the memory contents of a removable computer card in a computer system. The computer card includes a specialized random access memory and circuitry that...
5802131 Multiport serial access self-queuing memory switch  
A multiport switch buffers and transfers cells of digital data. It provides the ability to control the synchronization of the ports in a distributed manner. Each port is associated with a counter...
5793692 Integrated circuit memory with back end mode disable  
A memory circuit is described which can operate in one of a number of operating modes. The operating mode of the memory circuit can be changed in a non-volatile manner after the memory circuit is...
5793682 Circuit and method for disabling a bitline load  
The present invention concerns a circuit and method for disabling the load transistors from the bitlines of a memory array without requiring a fuse. After a particular column is disabled in a...
5793688 Method for multiple latency synchronous dynamic random access memory  
A multiple latency synchronous dynamic random access memory includes separate two and three latency control circuits driven by an input latch circuit. Commands received at the multiple latency...
5787040 Device for the protection of stored data  
A device for protection of data stored in a memory includes a supply voltage drop detection device to set an enabling signal in an active state when a supply voltage is below a threshold and a...
RE35847 Self-terminating data line driver  
The invention is a self-terminating helper flip-flop buffer circuit pertinent to a dynamic random access memory (DRAM) or static random access memory (SRAM) device. The invention turns off a device...
5777932 Semiconductor memory device test circuit having an improved compare signal generator circuit  
A test circuit for a DRAM is disclosed to preform a test operation in a page mode. The test circuit includes a compare control block 7A having a compare determination signal generator circuit 71...
5768211 Multi-port arbitration for high performance width expansion  
A multi-port memory device comprising a memory cell coupled to a first port and a second port. The second port receives write data for writing into the memory cell. The multi-port memory device...
5764592 External write pulse control method and structure  
A method and control circuit structure for externally controlling the width of a write pulse of a synchronous integrated circuit memory device is disclosed. The method and control circuit provide...
5749088 Memory card with erasure blocks and circuitry for selectively protecting the blocks from memory operations  
A memory card includes a plurality of memories, each having an array that includes a first block and a second block. Control circuitry is coupled to the array for controlling memory operations of...
5742546 Method and device for address decoding in an integrated circuit memory  
In a method for the decoding of the addresses of a memory, a pulse is generated at output of a filtering circuit at each change of address detected at the address bus to inhibit the address decoder...
5737262 Method and apparatus for avoiding back-to-back data rewrites to a memory array  
In a memory system, a first write address is initially loaded into a first latch and transferred to a second latch. A second write address is then loaded into the first address latch. The two...
5732030 Method and system for reduced column redundancy using a dual column select  
A semiconductor memory device (10) includes a plurality of row address inputs (RA0-RA8), and a plurality of column address input (CA0-CA8) lines. A plurality of main memory subarrays (122) include...
5724289 Nonvolatile semiconductor memory capable of selectively performing a pre-conditioning of threshold voltage before an erase self-test of memory cells and a method related therewith  
An electrically data chip-erasable nonvolatile semiconductor memory wherein a write instruction directing a pre-erase data write is disabled and then a one-time test data write and an automated...
5724295 Partitioned dynamic memory allowing substitution of a redundant circuit in any partition and using partial address disablement and disablement override  
A small number of redundant circuits are freely allocable to any of a plurality of partitions or systems within an integrated circuit, such as a large dynamic random access memory (DRAM) consistent...
5712815 Multiple bits per-cell flash EEPROM capable of concurrently programming and verifying memory cells and reference cells  
An improved programming structure for performing a program operation in an array of multiple bits-per-cell flash EEPROM memory cells is provided. A memory core array (12) includes a plurality of...
5710741 Power up intialization circuit responding to an input signal  
A power up pulse generator circuit generates a pulse of predetermined duration in spite of a slow rate of change of applied power supply voltage. The circuit has application to integrated logic...
5706232 Semiconductor memory with multiple clocking for test mode entry  
An integrated circuit having a normal operating mode and a special operating mode, such as a special test mode, is disclosed. The special test mode is enabled by a series of signals, such as...
5703810 DRAM for texture mapping  
A latch/mask mechanism that is located between the sense amplifiers of a DRAM and the data bus. The latch/mask mechanism decouples the data bus from the sense amplifiers and permits innovative,...
5699314 Video random access memory device and method implementing independent two we nibble control  
The invention is a monolithic video random access memory (VRAM) chip that has more than one write control pin which is used to segment the VRAM into banks or sub-chips having four DQ planes such...
5699306 Row redundancy for nonvolatile semiconductor memories  
A redundant circuit for EEPROMs which is capable of replacing defective normal memory cells with redundant memory cells in a wafer state as well as in a packaged state. The nonvolatile...
5696730 First read cycle circuit for semiconductor memory  
A novel circuit for initiating a first read cycle when power is first applied to the memory device is disclosed. The circuit compares the ramping up of the word line voltage signal to a stable...
5694611 Microcomputer including internal and direct external control of EEPROM and method of making the microcomputer  
A microcomputer including an EEPROM in which data may be stored and from which stored data may be read either under control of a central processing unit of the microcomputer or under direct...
5689453 Data storing apparatus having a memory capable of storing analog data  
A D/A converter converts input "n" bit digital data into discrete analog data by assigning each of the voltage values V 0 -V 2<2unull>s -1 to each "n" bit digital data. A non-volatile memory...
5680425 Self-queuing serial output port  
A multiport switch buffers and transfers cells of digital data. It provides the ability to control the synchronization of the ports in a distributed manner. Each port is associated with a counter...
5680569 Cache column timing control  
A cache which includes an integrated timing circuit through which the cache control passes thus allowing the timing of the storage circuit of the cache core to be adjusted.
5675534 Method and apparatus for preventing unauthorized access to nonvolatile memory in electronic encoders having a voltage level detection circuit  
According to the present invention, a method is provided for reading data from non-volatile memory in an electronic encoding device such that unauthorized access to the data is prevented. In one...
5673222 Nonvolatile semiconductor memory device  
An electrically erasable and rewritable semiconductor memory device including at least one memory block, comprising: a WP signal generator for generating a WP signal for controlling protection of...
5668973 Protection system for critical memory information  
A computer system for protecting memory comprising a processor having address outputs and executing a stored program, a memory having a control input, an address-decoder for providing a control...
5668760 Nonvolatile memory with a write protection circuit  
A nonvolatile memory includes a memory array and a control circuit having a command latch and a command decoder. The control circuit receives an output enable signal and a write enable signal to...
5666313 Semiconductor memory device with complete inhibition of boosting of word line drive signal and method thereof  
A word line drive signal generating circuit, which generates a word line drive signal RX to a selected word line, includes an RX generating circuit responsive to an external row address strobe...
5666516 Protected programmable memory cartridge having selective access circuitry  
A computer system for high-performance video and audio manipulations comprising a locked memory cartridge and an audio/video/compact disk (CD) drive controller/coprocessor. The computer system has...
5663921 Internal timing method and circuit for programmable memories  
A circuit generates flexible timing permitting a slow or fast overall timing configuration, and two configurations of the precharge and detecting intervals by providing both with two (short or...
5646902 Static random access memory device with low power dissipation  
A static random access memory device having a power-down timer for generating a power-down signal in response to a plurality of address transition detecting signals and data input detecting...
5646948 Apparatus for concurrently testing a plurality of semiconductor memories in parallel  
A test data pattern, an address pattern, and a control signal are supplied from a pattern generator to a test memory. Data read from the test memory is compared with expected data by an XOR gate....
5644538 Circuit and method for controllng the duration of pulses in a control signal from an electronic system  
A memory device (10) for use in an electronic system (12). The system (12) includes a processor (16) that produces a plurality of control signals. The memory device (10) includes a memory array...
5642318 Testing method for FIFOS  
The present invention provides a system for testing a memory array and corresponding support circuitry. The present invention provides a highly efficient testing mode to be entered that allows any...
5642480 Method and apparatus for enhanced security of a data processor  
A security system for a data processor. The data processor includes a register storage area (14) and a main memory storage area (16). The register storage area (14) and the main memory storage...
5638316 Memory apparatus  
The present invention relates to a memory apparatus to be able to do write protection and aims to protect data in a specified area in a memory device not to be easily rewritten. When address...
5629898 Dynamic memory device, a memory module, and a method of refreshing a dynamic memory device  
A period pulse corresponding to the shortest information retention time of those of dynamic memory cells is counted to form a refresh address to be assigned to a plurality of word lines. A carry...
5630090 Apparatus for and methods of providing a safe-stop mode for a microprocessor operating in a PSRAM-memory environment  
A microprocessor circuit including a microprocessor device and pseudo-static RAM memory further includes a switching circuit which is coupled to an NMI signal port and to a RESET signal port of the...
5629897 Synchronous semiconductor memory device having a mode requiring an internal clock signal and a mode not requiring the internal clock signal  
A refresh control circuit of a DLL circuit responds to an auto refresh detection signal AR and a self refresh detection signal SR to inhibit input of clock signals ECLK and RCLK to a phase...
5619463 Integrated circuit device and test method therefor  
An integrated circuit device includes an oscillator; a counter; a switch for selectively connecting the oscillator to the counter in a test mode; and an output circuit for providing the output...
5617351 Three-dimensional direct-write EEPROM arrays and fabrication methods  
A three-dimensional memory cell, suitable for electrically erasable programmable read only memories (EEPROMS), which has direct-write cell capability is disclosed. The memory cell is utilized in...
5604917 IC memory card having masking function for preventing writing of data into a fixed memory area  
An IC memory card includes an input/output unit attachable to or detachable from a host processing apparatus, a storage unit having a semiconductor memory for storing data, and a control unit for...
5598554 Multiport series memory component  
A multiport series memory component for a multiprocessor system comprising an integrated circuit having a random access memory of a predetermined width corresponding to a block of information, an...
5592641 Method and device for selectively locking write access to blocks in a memory array using write protect inputs and block enabled status  
A method and device for selectively enabling and disabling write access to flash blocks in a flash memory device. A lock command locks and unlocks a flash block in a flash array containing a...
5590083 Process of writing data from a data processor to a memory device register that is separate from the array  
A dual-port memory having an on-chip color register for storage of input data for use in multiple write cycles is disclosed. The color register is written to during a special cycle, which is...
5586077 Circuit device and corresponding method for resetting non-volatile and electrically programmable memory devices  
A method for generating a reset signal in an electrically programmable non-volatile storage device of a type which comprises a matrix of memory cells and a control logic portion being supplied a...
Matches 301 - 350 out of 734 < 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >