Matches 251 - 300 out of 734 < 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >
Match Document Document Title
6028804 Method and apparatus for 1-T SRAM compatible memory  
A method and apparatus for handling the refresh of a DRAM array so that the refresh has no effect on the external access. This allows an SRAM compatible memory to be built from DRAM (or...
6011734 Fuseless memory repair system and method of operation  
A Built-In Self Test (720) generates a BIST FAIL signal when a failure is detected at a specific address within a memory array (110). The address associated with the failure is stored in a latch...
6011737 DRAM with edge sense amplifiers which are activated along with sense amplifiers internal to the array during a read cycle  
A staggered bitline sense amplifier architecture utilizes a circuit to simulate the effect of a memory cell on each of the edge sense amplifiers not selected for connection to an activated memory...
6002619 Memory with read protected zones  
The invention relates to memories associated with the central processing units of microcomputers and more particularly, in such memories, to an architecture and device used to protect certain zones...
5999457 Semiconductor integrated circuit  
A semiconductor integrated circuit incorporating DRAM 2 and a logic circuit 3 includes a vector generating circuit 40 formed on the common substrate. Upon a burn-in process, the vector generating...
5991197 Semiconductor memory device having data protection feature  
A reset power down mode designating signal and first and second write protect signals are provided to a control circuit. According to the states of these external control signals, the status of...
5991849 Rewriting protection of a size varying first region of a reprogrammable non-volatile memory  
A program for rewriting data in an address region B is written in an address region A which can be rewritten by an external PROM writer. After resetting the microcomputer and rewriting the program...
5991207 Circuit configuration having a number of electronic circuit components  
A circuit configuration having a number of electronic circuit components. The operating state of the circuit components can be set to a reset or erase state by a predetermined control signal...
5986951 Address signal storage circuit of data repair controller  
An address signal storage circuit of a data repair controller is disclosed including: a level stabilizer for stabilizing a level of an input signal to a constant level by a level control signal...
5981971 Semiconductor ROM wafer test structure, and IC card  
In a semiconductor wafer (1), an internal circuit such as a ROM formed at a product region or a chip (2) can be tested via a test pad (5) formed on a scribe line (3). Here, since the test pad (5)...
5978915 Device for the protection of the access to memory words  
The access to memory words of an integrated circuit is protected by the creation of a decision table that receives addresses of instruction words and/or data words to be protected and that receives...
5973968 Apparatus and method for write protecting a programmable memory  
An apparatus and method for protecting memory content of a programmable memory is disclosed. A programmable memory, such as a random access memory (RAM), is configured to include a write protected...
5969999 Merged memory logic integrated circuits including buffers driven by adjustably delayed clock signals  
A merged memory logic (MML) integrated circuit includes an adjustable clock generator configured to receive a input clock signal and produce an adjustably delayed clock signal therefrom...
5970021 Synchronous semiconductor memory device having function of inhibiting output of invalid data  
A reset signal generation circuit included in an output control circuit ANDs a reset signal for resetting complementary data buses for transferring data to a second output stage at prescribed...
5956275 Memory-cell array and a method for repairing the same  
An array of memory cells are arranged in rows and columns. The array includes a plurality of cell plates that are each coupled to at least one of the memory cells. A generator produces a bias...
5956278 Semiconductor circuit device with internal power supply circuit  
In a DRAM (Dynamic Random Access Memory) having a voltage down converter, a driver transistor in the voltage down converter is connected parallel to another driver transistor, thus the driver...
5940328 Synchronous semiconductor device with memory chips in a module for controlling output of strobe signal for trigger in reading data  
One strobe signal (QS) is outputted from a group of two adjacent memory chips (MC(i-1), MCi) in each module. In each group, the second memory chip (MCi) receives a data mask signal (DQM(i-1))...
5940335 Prioritizing the repair of faults in a semiconductor memory device  
A variable size redundancy replacement (VSRR) arrangement for making a memory fault-tolerant. A redundancy array supporting the memory includes a plurality of variable size redundancy units, each...
5926434 Synchronous semiconductor memory device capable of reducing electricity consumption on standby  
An internal clock generating circuit 200 applies an external clock signal Ext.CLK to a clock buffer circuit 206 in response to activation of a chip select signal ext./CS. The clock buffer circuit...
5912849 Write Protection for a non-volatile memory  
A semiconductor memory device, divided into plural blocks, comprising: a memory array having a non-volatile memory element which makes the read cycle and the write cycle to be substantially...
5912848 Methods and apparatus for efficiently managing flash memory  
An electronic device, such as a radio telephone, includes a non-volatile memory, such as a Flash memory, for storing data and instructions, a non-volatile memory, typically a RAM, for storing data...
5907512 Mask write enablement for memory devices which permits selective masked enablement of plural segments  
A Mask Write mode for a semiconductor memory responds to an enable command. This permits a by-four chip to provide parity information for four sectors of memory. The invention allows the latching...
5903914 Memory access limiter for random access dynamic memories  
A memory access limiter for random access dynamic memory of data processing systems formed by several modules which can be independently activated in partial temporal superimposition, each by a...
5901093 Redundancy architecture and method for block write access cycles permitting defective memory line replacement  
An invention is disclosed which implements bit line redundancy in a memory module, such as a dynamic random access memory (DRAM), in accordance with a block write operation. The block write...
5901092 Memory device having pipelined access and method for pipelining data access  
In one embodiment of the invention, a word line is coupled to a row of memory cells, and some of the memory cells are accessed before the firing signal has propagated all the way to the back end of...
5901096 Semiconductor memory device capable of disconnecting an internal booster power supply from a selected word line in response to a test signal and testing method therefor  
There is provided disconnecting circuit for disconnecting an internal boosted power supply from a word line. At the time of testing, one of a plurality of word lines is selected therefrom and data...
5901107 Semiconductor memory device selection method and circuit for embodying the same  
Only a first EEPROM 2 can output data according to an output signal of a selector circuit 5 when a "High" logical value signal and a "Low" logical value signal are output from first and second...
5896325 IC card with error processing unit for sense amplifiers  
An IC card having a memory for receiving data from and sending data to a data reader/writer includes a reading-completion detection circuit for detecting if each sense amplifier in the IC card has...
5892711 Sector protection circuit for a flash memory device  
There is disclosed a sector protecting circuit for a flash memory device. In order to prevent loss of data from a cell for sector protection, the sector protecting circuit for a flash memory device...
5890199 Data processor incorporating a ferroelectric memory array selectably configurable as read/write and read only memory  
A data processor incorporating a memory array which is selectably configurable as either read/write or read only memory or the combination of both read/write and read only memory includes a memory...
5886941 Address decoder and address decoding method  
There is provided an address decoder which allows a high-speed operation without causing a malfunction. When a pre-charge signal is in a state of being set at a logical level of "0", an address...
5880992 Electrically erasable and programmable read only memory  
An electrically erasable and programmable read only memory (EEPROM) device is disclosed. The EEPROM device includes a memory array coupled to an address bus and a data bus; a register located in a...
5881002 Nonvolatile memory control circuit  
A nonvolatile control circuit reads out data from a nonvolatile memory at a predetermined address upon power-up. When the read-out data is data that instructs inhibition of at least one of...
5880997 Bubbleback for FIFOS  
A method and apparatus for greatly simplifying the circuitry needed to handle the bubbleback situations in FIFO memories includes an additional row of cells added to the memory array. By adding an...
5875121 Register selection system and method  
A register selection system increases a speed for selection of memory registers when selection is based upon a constant K defined by a sum of two numbers. The register selection system includes a...
5872742 Staggered pipeline access scheme for synchronous random access memory  
A static random access memory (SRAM) (10) operating in synchronism with an external clock is disclosed. The synchronous SRAM (10) includes a transparent address circuit (14) for decoding an...
5867446 Synchronous semiconductor memory device  
Memory arrays are divided into banks which can be operated independent from each other. Read data storing registers and write data storing registers operating independent from each other are...
5867437 Static random access memory with improved write recovery procedure  
A method and apparatus for reading and writing data into a random access memory array having a dummy bit. The method includes the steps of providing a clock signal having two edges, one going from...
5848022 Address enable circuit in synchronous SRAM  
A novel address enable circuit for use in a synchronous memory that includes a memory core. The address enable circuit includes an address latching circuit that outputs a synchronized address and...
5844848 Integrated circuit memory devices having improved data masking capability  
Integrated circuit memory devices having improved data masking capability include a memory cell array having a plurality of bit lines coupled thereto and a first sense amplifier that has first and...
5838613 Semiconductor memory device having security function  
A non-volatile semiconductor memory device includes first, second and third comparators, counter and ring oscillator. The first comparator compares an input address with an access inhibition...
5835422 Circuit and method for generating a control signal for a memory device  
A memory device (10) for use in an electronic system (12). The system (12) includes a processor (16) that produces a plurality of control signals. The memory device (10) includes a memory array...
5831911 Semiconductor memory device for reducing a static current  
Present invention is to provide an semiconductor memory device capable of reducing a static current by turning off a bit line pull-up transistor at a write operation. A cell array divided to a...
5822085 Data communication system for writing or reading data to/from image forming apparatus at a remote distance and data communicating apparatus constructing such a system  
In a remote registry system, an object of the invention is to read and write memory data as binary data. A memory access method is limited for a data read inhibit area or a write inhibit area. A...
5818775 Static ram with reduced power consumption  
The invention relates to a memory comprising a matrix of memory cells; a plurality of gates for transmitting respective selection outputs of a row decoder to respective rows of the matrix; a dummy...
5818771 Semiconductor memory device  
A semiconductor memory device, divided into plural blocks, includes a memory array having a non-volatile memory element in which address access times for the read cycle and the write cycle are...
5812446 Method and apparatus for the protection of non-volatile memory zones  
The disclosure relates to integrated circuits and methods in which it is desired to implement a partition of a memory between a protected zone and a non-protected zone, the dimensions of the...
5812488 Synchronous burst extended data out dram  
An integrated circuit memory device is described which can operate at high data speeds. The memory device can either store or retrieve data from the memory in a burst access operation. The burst...
5809553 Nonvolatile memory devices including lockable word line cells  
Nonvolatile memory devices and methods include an array of nonvolatile memory cells which are arranged in a plurality of rows and a plurality of columns. A plurality of word lines are also...
5802583 Sysyem and method providing selective write protection for individual blocks of memory in a non-volatile memory device  
A system and method for selective write protection for a non-volatile memory device which comprises a superset of the existing JEDEC 21-C standard and in which user definable portions of a...
Matches 251 - 300 out of 734 < 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >