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7613054 SRAM device with enhanced read/write operations  
An SRAM device includes: a first group of memory cells connected to a first local bit line and a first local complementary bit line for accessing data nodes thereof; a second group of memory cells...
7609573 Embedded memory databus architecture  
A dynamic random access memory (DRAM) having pairs of bitlines, each pair being connected to a first bit line sense amplifier, wordlines crossing the bitlines pairs forming an array, charge storage...
7609542 Implementing enhanced SRAM read performance sort ring oscillator (PSRO)  
A method and apparatus including a static random access memory (SRAM) cell implement an enhanced SRAM read performance sort ring oscillator (PSRO), and a design structure on which the subject...
7606087 Semiconductor memory device and over driving method thereof  
A semiconductor memory device may include a power line, an over driver, and/or an internal voltage driver. The power line may be connected to at least one sense amplifier. The at least one sense...
7606062 Ultra low voltage and minimum operating voltage tolerant register file  
Methods and apparatus relating ultra-low voltage memory bit cells are described. In an embodiment, an ultra-low voltage memory device is provided using redundant paths to data storage nodes...
7602657 Semiconductor memory device having floating body cell  
A semiconductor memory device includes a sense amplifier for the FBC, a first node and a second node can be disconnected from each other by a first isolation transistor. A third node and a fourth...
7602653 Multimode data buffer and method for controlling propagation delay time  
A data buffer, such as a data strobe input buffer or a data input buffer, which may operate in multiple modes, such as a single mode (SM) and a dual mode (DM) and where the mode is selected by...
7596040 Methods and apparatus for improved write characteristics in a low voltage SRAM  
Methods and apparatus provide for writing data into and reading data from an anti-parallel storage circuit of an SRAM memory cell via a true bit line (BLT) and a complementary bit line (BLC); and...
7573769 Enable signal generator counteracting delay variations for producing a constant sense amplifier enable signal and methods thereof  
A sense amplifier enable signal generator has two stages. Each stage offsets transistor performance variation in the other stage to produce an enable signal output relatively immune from the...
7573755 Data amplifying circuit for semiconductor integrated circuit  
A data amplifying circuit for a semiconductor integrated circuit including a controller configured to generate a control signal for adjusting an amplification step in response to a test signal, and...
7567477 Bias sensing in sense amplifiers through a voltage-coupling/decoupling device  
Voltage coupling/decoupling devices are provided within DRAM devices for improving the bias sensing of sense amplifiers and thus the refresh performance. The voltage coupling/decoupling devices...
7567452 Multi-level dynamic memory device having open bit line structure and method of driving the same  
A multi-level dynamic memory device having an open bit line structure is disclosed. The multi-level dynamic memory device includes a plurality of word lines; a plurality of bit lines provided in an...
7564726 Semiconductor memory device  
A semiconductor memory device includes a selector line selection circuit for selecting, in a read operation, a selector line for connecting a first main bit line connected to the sense amplifier...
7542334 Bistable latch circuit implemented with nanotube-based switching elements  
A nanotube-based switching element includes an input node, an output node, and a nanotube channel element having at least one electrically conductive nanotube. A control structure is disposed in...
7539070 Semiconductor memory apparatus and method of resetting input/output lines of the same  
A semiconductor memory apparatus includes a plurality of unit cell blocks formed in row and column directions, at least a pair of first input and output lines formed at predetermined intervals in...
7535750 Asymmetrical random access memory cell, and a memory comprising asymmetrical memory cells  
Asymmetrical random access memory cell ( 1 ) including cross coupled inverters ( 2, 3 ) which are driven at their nodes ( 22, 32 ) by separate bit-lines (blt, blc) of a pair of complementary...
7529144 Hierarchical semiconductor memory device capable of carrying out a disturb refresh test on a memory array basis  
A semiconductor memory device of the present invention provides, in a memory having an hierarchical bit line structure, a test mode which causes all switches for selecting hierarchical bit lines...
7525867 Storage circuit and method therefor  
Storage circuits ( 180 - 183 and 280 - 281 ) may be used for low power operation while allowing fast read access. In one embodiment (e.g. circuit 100 ), shared complementary write bit lines (...
7515486 Multimode data buffer and method for controlling propagation delay time  
A data buffer, such as a data strobe input buffer or a data input buffer, which may operate in multiple modes, such as a single mode (SM) and a dual mode (DM) and where the mode is selected by...
7512019 High speed digital signal input buffer and method using pulsed positive feedback  
An input buffer generates an output signal corresponding to a digital input signal. The input buffer is coupled to a feedback circuit. The feedback circuit initially couples a positive feedback...
7505348 Balanced and bi-directional bit line paths for memory arrays with programmable memory cells  
An improved memory system incorporates an array of memory cells that are subjected to minimal location dependent power variations and, optionally, allows for bi-directional random access of...
7499310 Bit line voltage supply circuit in semiconductor memory device and voltage supplying method therefor  
There is provided a bit line voltage supply circuit for reducing leakage current flowing from bit lines to a memory cell without substantially deteriorating the performance of a semiconductor...
7489588 Semiconductor memory device having a main amplifier equipped with a current control circuit in a burst read operation  
A column circuit that amplifies signals read from a sense amplifier array SAA to local input/output lines LIO in sub-amplifiers SAMP to transfer the amplified signals to main input/output lines MIO...
7486580 Wide databus architecture  
A dynamic random access memory (DRAM) having pairs of bitlines, each pair being connected to a first bit line sense amplifier, wordlines crossing the bitlines pairs forming an array, charge storage...
7480199 Method for low power refresh of a dynamic random access memory using a slower refresh rate than a normal refresh rate  
A method and system for operating a DRAM device in either a high power, full density mode or a low power, half density mode. In the full density mode, each data bit is stored in a single memory...
7480189 Cross-coupled write circuit  
A write circuit structure may be used to transfer data between global bit lines and local bit lines of a cache. The write circuit structure located between the hierarchical bit lines may be buffers...
7480170 Method and apparatus for implementing enhanced SRAM read performance sort ring oscillator (PSRO)  
A method and apparatus including a static random access memory (SRAM) cell implement an enhanced SRAM read performance sort ring oscillator (PSRO). A pair of parallel reverse polarity connected...
7474548 Semiconductor memory device and method for manufacturing the same  
A semiconductor memory device includes: a memory cell array region formed in a semiconductor region of a first conductivity type and having a plurality of memory cells arranged in rows and columns;...
7463537 Global bit select circuit interface with dual read and write bit line pairs  
A domino SRAM global bit select circuit provides an interface between dual global read and write bit line pairs to a “local bit select” circuit.
7457171 Integrated semiconductor memory with transmission of data via a data interface  
During a read access to a memory cell array of an integrated semiconductor memory device, data of a data word is fed to a data generator circuit which can be operated in the operating modes of...
7450454 Low voltage data path in memory array  
A data path of a memory is from an array of the memory, through a sense amplifier, through NOR gates, through N channel transistors, and through a latch that provides an output. The sense amplifier...
7436720 Semiconductor memory device  
A semiconductor memory device includes plates accessed by different row addresses and a sense amplifier column between the adjacent plates. The sense amplifier column is a mixture of...
7436696 Read-preferred SRAM cell design  
A read-preferred SRAM cell includes a pull-up MOS device having a first drive current, a pull-down MOS device coupled to the pull-up MOS device, the pull-down MOS device having a second drive...
7433223 Memory devices including floating body transistor capacitorless memory cells and related methods  
In one aspect, a semiconductor memory device is provided which includes complementary first and second bit lines, a unit memory cell including complementary first and second floating body...
7433217 Content addressable memory cell configurable between multiple modes and method therefor  
A CAM cell ( 200 ) can include a compare section ( 206 ) and a configuration section ( 208 ). In a binary mode of operation, two compare data values can be driven on value lines VL1 to VL4 ( 216 -...
7430147 Precharge apparatus  
A precharge circuit prevents voltage dropping of a local input/output line in a semiconductor memory apparatus. The precharge circuit includes at least one pair of pull-up and pull-down precharge...
7414906 Memory component having a novel arrangement of the bit lines  
A memory component comprises a plurality of bit lines, on which memory cells are arranged, and a plurality of sense amplifiers, which are arranged in a row, each sense amplifier being connected to...
7411844 Semiconductor memory device having a redundancy information memory directly connected to a redundancy control circuit  
A semiconductor memory device (M) includes a memory array (MA) having a plurality of memory cells, a redundancy array (RA) having a plurality of memory cells, a non-volatile redundancy information...
7411813 Semiconductor device  
In case that data are written in a flip-flop circuit by inverting the voltage to be supplied to a pair of write bit lines, the peak of the current waveform flowing in the pair of write bit lines is...
7408813 Block erase for volatile memory  
A system and method for erasing a block of data in a plurality of memory cells includes clamping one of a digit line and an I/O line in a sensing circuit of a memory device to a fixed logic level....
7397722 Multiple block memory with complementary data path  
A memory has a first memory block, a second memory block, a data bus, a first sense amplifier, a second sense amplifier, a first circuit, and a second circuit. The first sense amplifier is coupled...
7391643 Semiconductor memory device and writing method thereof  
To provide a semiconductor memory device comprising a phase-change memory and having high compatibility with DRAM interface. The memory cell array 18 comprises a memory cell that includes a...
7388773 Random access memory with a plurality of symmetrical memory cells  
The invention proposes a Random Access Memory ( 1 ) with a plurality of symmetrical memory cells ( 2 ) which are connected in groups to complementary bit lines (blc, blt), and the complementary bit...
7379341 Loading data with error detection in a power on sequence of flash memory device  
A method of performing a power on sequence for a flash memory includes applying device voltage to the flash memory and loading nonvolatile memory data and nonvolatile memory complementary data to a...
7362624 Transistor level shifter circuit  
A transistor level shifter circuit constituted by a plurality of PMOS TFT is included. The transistor level shifter circuit primarily includes a conversion circuit, a first amplifier circuit, and a...
7359268 Semiconductor memory device for low voltage  
A semiconductor memory device includes a read amplifying unit for transferring a data from a local data line pair to a global data line as a read data; a write driver for transferring a write data...
7345909 Low-power SRAM memory cell  
An SRAM memory cell that has a relatively small power consumption when writing a write value of ‘0’ to the memory cell includes cross-coupled first and second inverters, at least one read...
7339839 Triggering of IO equilibrating ending signal with firing of column access signal  
A method and apparatus for improving time between row address latching and column address latching (tRCD) by allowing the pull-up of the IO lines during a READ burst to end upon the firing of a...
RE40132 Large scale integrated circuit with sense amplifier circuits for low voltage operation  
Disclosed is a one-chip ULSI which can carry out the fixed operation in a wide range of power supply voltage (1 V to 5.5 V). This one-chip ULSI is composed of a voltage converter circuit(s) which...
7336552 Sense amplifier connecting/disconnecting circuit arrangement and method for operating such a circuit arrangement  
An apparatus and method for operating a sense amplifier connecting/disconnecting circuit arrangement, in particular for a semiconductor memory device, including a switching device for...
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