Matches 1 - 50 out of 108 1 2 3 >


Match Document Document Title
8130571 Semiconductor integrated circuit  
A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed In an address space of the central processing unit. The nonvolatile memory area...
8130579 Memory device and method of operation thereof  
Memory devices and methods of operating a memory cell are disclosed in which a bitline can be grounded after charge sharing with an electrically floating ground line and before writing data to the...
8120974 Nonvolatile semiconductor memory device  
A nonvolatile semiconductor memory device comprising: a memory cell array in which two bit lines are provided to each one bit of input data, and memory cells each including an anti-fuse element are...
8098539 Hybrid single and dual channel DDR interface scheme by interleaving address/control signals during dual channel operation  
A memory structure is described. In one embodiment, the memory structure comprises a memory controller configured to receive a clock signal and to be coupled to a plurality of memory modules via a...
8072821 Semiconductor memory device that can perform successive accesses  
To provide an input/output circuit that includes a write path to which write data is supplied and a read path to which read data is supplied and first and second data lines that connect the...
8064270 Semiconductor integrated circuit device  
A semiconductor integrated circuit device includes a data circuit and a group of bit line application voltage terminals to which different voltages are applied. The data circuit holds program data...
8064268 Method and system for a serial peripheral interface  
An integrated circuit device includes a serial peripheral interface adapted for receiving a first command supporting an address of a first configuration, wherein the serial peripheral interface...
8050082 Two-stage 8T SRAM cell design  
An integrated circuit device includes a first word-line; a second word-line; a first bit-line; and a static random access memory (SRAM) cell. The SRAM cell includes a storage node; a pull-up...
8032688 Micro-tile memory interfaces  
In one embodiment of the invention, a memory integrated circuit is provided including an address decoder to selectively access memory cells within a memory array; a mode register with bit storage...
8004926 System and method for memory array decoding  
A memory system includes Q memory blocks that each include M memory sub-blocks. The memory system also includes Q word line decoders that each are associated with a different one of the Q memory...
7978545 Semiconductor integrated circuit  
A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed in an address space of the central processing unit. The nonvolatile memory area...
7940597 Semiconductor memory device and parallel test method of the same  
Semiconductor memory device and parallel test method of the same. The test includes writing data into multiple memory banks simultaneously, reading the data from a portion of the memory banks,...
7920431 Asynchronous/synchronous interface  
The present disclosure includes methods, and circuits, for operating a memory device. One method embodiment for operating a memory device includes controlling data transfer through a memory...
7872936 System and method for packaged memory  
In one embodiment, a memory system is disclosed. The memory system has at least one memory chip having an address and data interface coupled to an internal address and data bus, and a memory...
7872926 Input buffer and method with AC positive feedback, and a memory device and computer system using same  
An input buffer having a comparator that receives an input signal, a reference signal and a positive feedback. The comparator compares the input signal relative to the reference signal and...
7864603 Memory elements with leakage compensation  
Integrated circuits with memory elements are provided. The memory elements may be arranged in an array. Data lines may be used to load data into the memory elements and may be used to read data...
7859922 Programming a flash memory device  
An initial verify read operation is performed after each programming pulse. The verify voltage starts at an initial verify voltage for the first word line and increases for each word line that is...
7848135 Piezo-driven non-volatile memory cell with hysteretic resistance  
A piezoelectrically programmed, non-volatile memory cell structure includes a programmable piezo-resistive hysteretic material (PRHM) that is capable of being interconverted between a low...
7830734 Asymetric data path position and delays technique enabling high speed access in integrated circuit memory devices  
An asymmetric data path position and delays technique enabling high speed access in integrated circuit memory devices which is asymmetric in terms of the delay from the array to the I/O buffers...
7821824 Semiconductor integrated circuit having buses with different data transfer rates  
A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed in an address space of the central processing unit. The nonvolatile memory area...
7715254 Data output circuit of semiconductor memory apparatus and method of controlling the same  
The data output circuit for a semiconductor memory apparatus includes a first control signal generating unit configured to generate a first control signal according to a row address and a read...
7692946 Memory array on more than one die  
For one disclosed embodiment, an apparatus may comprise a first die including a first plurality of memory cells for a memory array and a second die including a second plurality of memory cells for...
7668036 Apparatus for controlling GIO line and control method thereof  
A control apparatus of a GIO line includes a plurality of GIO line termination units, and a GIO control unit for generating a control signal to activate an operation of a specific one of the...
7663951 Semiconductor memory apparatus  
A semiconductor memory apparatus includes a main bank configured to combine a first sub bank and a second sub bank. A center bitline sense amplifier array is arranged in a region where the first...
7646628 Toggle magnetic random access memory and write method of toggle magnetic random access memory  
A toggle magnetic random access memory includes a first memory array, a second memory array and a controller. The first memory array includes a plurality of first memory cells including...
7630271 Semiconductor memory device including a column decoder array  
A semiconductor memory device is presented that exhibits an enhanced read/write data retrieval efficiency brought about in part by a uniquely shared column array communication scheme. The...
7626878 Active bit line charge keeper  
One embodiment of the present invention sets forth an active bit line charge keeper circuit for improving the reliability of a static random access memory (SRAM) circuit. The active bit line charge...
7626872 Semiconductor memory device and its driving method  
A semiconductor memory device includes a data transfer line for read, a data signal transfer unit, a reset controller, and a data signal transfer unit for write. The data signal transfer unit for...
7613886 Methods and apparatus for synchronizing data access to a local memory in a multi-processor system  
Methods and apparatus provide for receiving a request from an initiating device to initiate a data transfer into a local memory for execution of one or more programs therein, the local memory being...
7613062 Semiconductor memory device in which data is stored in nonvolatile state, by using semiconductor elements of metal oxide semiconductor (MOS) structure  
A semiconductor memory device includes a memory element, a first data line and a second data line, a first selection transistor, and a second selection transistor. The memory element includes a...
7613049 Method and system for a serial peripheral interface  
A method for dual I/O data read in an integrated circuit which includes a serial peripheral interface memory device. In an embodiment, the memory device includes a clock signal, a plurality of...
7609566 Semiconductor memory device  
A semiconductor memory device includes a charge pumping circuit, a level sensor, an oscillator, and a pumping control signal generator. The charge pumping circuit performs a negative-pumping...
7602656 Power supply control circuit and controlling method thereof  
A power supply control circuit and a control method secure an accurate operation of a GIO in a burst data transmission having a high compression rate. The power supply control circuit of a...
7577013 Storage units and register file using the same  
A storage unit capable of retaining data during sleep mode. The storage unit includes a first latch composed of first and second inverters and a second latch composed of the first inverter and a...
7516027 Configurable voltage regulator  
A production testing system for testing an integrated circuit comprises a control module that generates a setpoint and a setpoint range. A configurable integrated circuit receives the setpoint and...
7486571 Semiconductor memory device  
Disclosed herein is a semiconductor memory device including, a memory array with memory cells array-like arranged, a read bit line connected to a data output node of the memory cells and shared by...
7471575 Non-volatile memory and method with shared processing for an aggregate of read/write circuits  
A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has an architecture that reduces redundancy in the multiple...
7468902 SRAM device with a low operation voltage  
An SRAM cell includes: a first PMOS transistor having a source coupled to a supply voltage; a second PMOS transistor having a source coupled to the supply voltage, a drain coupled to a gate of the...
7466607 Memory access system and method using de-coupled read and write circuits  
A de-coupled memory access system including a memory access control circuit is configured to generate first and second independent, de-coupled time references. The memory access control circuit...
7436696 Read-preferred SRAM cell design  
A read-preferred SRAM cell includes a pull-up MOS device having a first drive current, a pull-down MOS device coupled to the pull-up MOS device, the pull-down MOS device having a second drive...
7426607 Memory system and method of operating memory system  
A random access memory system has a memory controller, a first memory device, a second memory device, and a memory bus. The memory controller is configured to control access to a plurality of...
7286382 Segmented dataline scheme in a memory with enhanced full fault coverage memory cell testability  
A memory includes a plurality of row segments, with each row segment having a number of memory cells coupled to a corresponding dataline segment pair. Dataline driver circuits are provided between...
7200730 Method of operating a memory at high speed using a cycle ready status output signal  
A self-clocking memory device comprises a memory array, a memory input circuit, and a memory control circuit. The memory input circuit is operable to receive an input clock signal and generate a...
7149916 Method for time-domain synchronization across a bit-sliced data path design  
A bit slice data path design is provided. Multiple chips are coupled to a data bus and configured to process a slice of data for the data bus. One chip in the design is designated as a master chip...
7120075 Multi-FIFO integrated circuit devices that support multi-queue operating modes with enhanced write path and read path queue switching  
An integrated circuit chip includes a plurality of independent FIFO memory devices that are each configured to support all four combinations of DDR and SDR write modes and DDR and SDR read modes...
7106620 Memory cell having improved read stability  
A memory cell for use in a memory array includes a storage element for storing a logical state of the memory cell, a write circuit and a read circuit. The write circuit is operative to selectively...
7057963 Dual port SRAM memory  
The layout structure of a dual port SRAM (Static Random Access Memory) includes a read bit line adjacently positioned to a complementary read bit line, and a write bit line positioned adjacent to a...
7023721 Semiconductor integrated circuit device  
A semiconductor integrated circuit device including a plurality of memory cells, each having a storage MOSFET holding information in a gate of the storage MOSFET, a write transistor supplying a...
7009892 Semiconductor memory device and portable electronic apparatus  
A semiconductor memory device includes a control logic circuit for generating read selection signals each selecting one plane for reading and write selection signals each selecting one plane for...
7006404 Memory device with increased data throughput  
A memory device (200) can include memory cell arrays (202-a and 202-b) accessed according to phase shifted clock signals. Memory cell array (202-a) can be accessed at double data rates essentially...
Matches 1 - 50 out of 108 1 2 3 >