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7379354 Methods and apparatus to provide voltage control for SRAM write assist circuits  
Methods and apparatus to control voltage output of a write assist circuit are disclosed. An example method includes regulating pull down voltage from a write assist circuit having a write assist...
7289379 Memory devices and methods of operation thereof using interdependent sense amplifier control  
A memory device includes a control circuit configured to disable a local input/output line sense amplifier responsive to a global input/output line sense amplifier enable signal. The device may...
7289372 Dual-port memory array using shared write drivers and read sense amplifiers  
Dual port memory blocks that have a reduced layout area are provided. The write drivers and sense amplifiers are shared between the dual ports to reduce the number of write drivers and sense...
7289371 Semiconductor memory device and electronic equipment  
A semiconductor memory device has a memory cell array in which a plurality of nonvolatile memory cells are arranged. The memory device also has word lines, bit lines connected with the memory cells...
7286415 Semiconductor memory devices having a dual port mode and methods of operating the same  
A memory device having a dual port function includes a memory cell array and a switching unit. The memory cell array has a first port and a second port. The switching unit assigns first data...
7277330 Nonvolatile semiconductor memory device having improved redundancy relieving rate  
In a memory cell array of an MRAM, a normal memory cell is compared with a reference memory cell which holds a reference value, thereby storing data of one bit per cell. Two spare memory cells...
7274605 Per-bit set-up and hold time adjustment for double-data rate synchronous DRAM  
A synchronous double-data-rate semiconductor memory device is adapted to receive write data on both the rising and falling edges of a data strobe signal derived from an externally-applied system...
7269090 Memory access with consecutive addresses corresponding to different rows  
A memory system ( 200 ) has an array of addressable storage elements ( 210 ) arranged in a plurality of rows and a plurality of columns, and decoding circuitry ( 220, 230 ) coupled to the array of...
7269084 Semiconductor memory device  
The disclosure concerns a semiconductor memory device that includes memory cells that store data by accumulating or discharging an electric charge; memory cell arrays having a plurality of the...
7263025 Semiconductor memory device for stably controlling power mode at high frequency and method of controlling power mode thereof  
The present invention relates to a semiconductor memory device. When a device exits from power mode, after a time until an instruction/address receive control signal substantially turns on or off...
7260020 Synchronous global controller for enhanced pipelining  
The present invention relates to a system and method for processing the read and write operations in a memory architecture. The system processing the read and write operations includes at least one...
7251193 Pseudo-dual port memory where ratio of first to second memory access is clock duty cycle independent  
A pseudo-dual port memory performs both a first memory access operation and a second memory access operation in a single period of an externally supplied clock signal CLK. The signal CLK is used to...
7251149 Semiconductor memory device provided with a write column selection switch and a read column selection switch separately  
A Y selection line for write for controlling operations of a column selection switch within a write amplifier and a Y selection line for read for controlling operations of a column selection switch...
7221607 Multi-port memory systems and methods for bit line coupling  
Systems and methods provide bit line coupling detection techniques for multi-port memory applications. For example, in accordance with an embodiment of the present invention, a memory includes at...
7218562 Recovering bit lines in a memory array after stopped clock operation  
In one embodiment, an apparatus comprises a plurality of memory cells; first and second bit lines coupled to the plurality of memory cells; a first and second bit line precharge circuits coupled to...
7218557 Method and apparatus for adaptive determination of timing signals on a high speed parallel bus  
Methods and apparatus are provided for adaptive determination of timing signals, such as on a high speed parallel bus. The invention adaptively determines a timing signal having a first edge with...
7215251 Method and apparatus for controlled persistent ID flag for RFID applications  
A Radio-Frequency Identification (RFID) transponder is provided. The RFID transponder may include a basic ID flag circuit having a VDD voltage node, an output voltage node, and a capacitor coupled...
7203809 Data transfer control method, and peripheral circuit, data processor and processing system for the method  
A memory 1 performs its internal operation in response to access requests ( 200, 201 and 202 ) of a CPU 2 in synchronism with the oscillated output of a self-excited oscillator 102 ...
7200064 Apparatus and method for providing a reprogrammable electrically programmable fuse  
An apparatus and method for providing a reprogrammable electrically programmable fuse (eFuse) are provided. With the apparatus and method, a pair of eFuses are provided coupled to programming...
7200027 Ferroelectric memory reference generator systems using staging capacitors  
Reference generator systems ( 108, 130 ) and methods ( 200 ) are presented for providing bitline reference voltages for memory access operations in a ferroelectric memory device ( 102 ). The...
7193913 Sense amplifier circuit and read/write method for semiconductor memory device  
A sense amplifier circuit comprising a local I/O line pair, a global I/O line pair, a write amplification unit for amplifying and transferring data output from the global I/O line pair to the local...
7190632 Semiconductor memory device having improved column selection lines and method of driving the same  
A semiconductor memory device includes first and second global column selection lines via which first and second global column selection signals are respectively transmitted to select a column of a...
7187613 Method and apparatus for dynamically configuring redundant area of non-volatile memory  
A method and an apparatus for dynamically configuring the redundant areas of a non-volatile memory is provided wherein each page of a memory is configured into a plurality of data areas and a...
7187593 Control system; control apparatus; storage device and computer program product  
A reading/writing process control unit for instructing a reading/writing process and an erasing process control unit for instructing an erasing process are provided separately and each is connected...
7184359 System and method for staging concurrent accesses to a memory address location via a single port using a high speed sampling clock  
A memory device, apparatus and method are provided for accessing memory cells. The device, apparatus, and method allow two or more electronic subsystems with corresponding external ports to access...
7184346 Memory cell sensing with low noise generation  
Various methods, apparatuses and systems in which a memory uses a noise reduction circuit to sense groups of memory cells. The memory has a plurality of memory cells organized into groups of memory...
7184323 4N pre-fetch memory data transfer system  
A semiconductor storage device has a data transfer circuit capable of reducing the latency, including a control circuit for frequency-dividing external clock signal to generate readout clocks,...
7184295 Memory device  
A memory device is provided in which recording of multi-valued data can be performed at a high speed and the recording of multi-valued data can be performed with a drive circuit having...
7180808 Semiconductor memory device for performing refresh operation  
A memory device according to the present invention includes multiple refresh modes and a refresh controller. A first refresh mode can respectively select one more memory block among a plurality of...
7170797 Test data topology write to memory using latched sense amplifier data and row address scrambling  
For one or more disclosed embodiments, a test data topology may be written to memory by writing data into an initial row of memory cells. The writing of data comprises latching data in a plurality...
7164615 Semiconductor memory device performing auto refresh in the self refresh mode  
Method and apparatus for use with multi-bank Synchronous Dynamic Random Access Memory (SDRAM) circuits, modules, and memory systems are disclosed. In one described embodiment, an SDRAM circuit...
7164610 Microcomputer having a flush memory that can be temporarily interrupted during an erase process  
A microcomputer with a built-in non-volatile semiconductor memory, which can automatically perform a work of temporarily interrupting automatic writing or automatic erase and accepting an...
7161843 Semiconductor memory device and method for writing data  
A semiconductor memory device, comprising a memory array including a plurality of memory cells capable of storing data of at least 1 bit, includes a data write control section for controlling a...
7161825 Memory device, circuits and methods for operating a memory device  
A ferroelectric memory comprises a plurality of memory cells and circuitry to sense data thereof. Power supply decoupling circuitry may decouple supplies of the memory device during a portion of...
7158429 System for read path acceleration  
A system for read path acceleration has a first strobe reset circuit coupled to a first local amplifier. A second strobe reset circuit is coupled to a second local amplifier. A main amplifier is...
7158426 Method for testing an integrated semiconductor memory  
An integrated semiconductor memory can be operated in a normal operating state synchronously with a control clock. In the test operating state, the integrated semiconductor memory is driven...
7154804 Semiconductor integrated circuit and IC card  
A semiconductor integrated circuit has a memory which can enter active state or standby state, and the memory has voltage generation circuits for bit lines and source lines with which memory cells...
7151687 Ferroelectric memory device, electronic apparatus and driving method  
A ferroelectric memory device that is equipped with a cell array provided with a plurality of memory cells each having a first ferroelectric capacitor and a second ferroelectric capacitor that are...
7149130 Page buffer circuit of flash memory device with reduced consumption power  
A page buffer circuit of a flash memory device has small consumption power. The page buffer circuit utilizes different voltages are supplied to the latch circuits in the standby and normal modes to...
7145829 Single cycle refresh of multi-port dynamic random access memory (DRAM)  
A multi-port DRAM having refresh cycles interleaved with normal read and write operations implements a single cycle refresh sequence by deferring the write portion of the sequence until the next...
7139202 Semiconductor storage device, mobile electronic apparatus, and method for controlling the semiconductor storage device  
A semiconductor storage device is provided, which comprises a memory array comprising memory elements, a write state machine for applying a first voltage for performing a write or erase operation,...
7136308 Efficient method of data transfer between register files and memories  
A memory system includes an active storage circuit and at least one base storage circuit. The at least one base storage circuit is coupled to the active storage circuit though at least one pass...
7126857 Storage subsystem with embedded circuit for protecting against anomalies in power signal from host  
A storage subsystem, such as a flash memory card, includes a voltage detection circuit that monitors the power signal from a host system to detect anomalies. The voltage detection circuit responds...
7126842 Deglitching circuits for a radiation-hardened static random access memory based programmable architecture  
The present invention comprises a device and a method for a deglitching circuit for a radiation tolerant static random access memory (SRAM) based field programmable gate array. The deglitching...
7120084 Integrated memory controller  
A system and circuit for reading and writing data to a buffer memory, which is Synchronous Dynamic Random access Memory (“SDRAM”), or Double Data Rate-Synchronous Dynamic Random Access Memory...
7116579 Semiconductor storage device and mobile electronic apparatus  
A semiconductor storage device is provided, which comprises a memory array comprising memory elements, a write state machine for performing a sequence of a program or erase operation with respect...
7114047 Data storage medium with certification data  
A data storage medium has a first memory area that is read-only and stores first certification data that is unique to the data storage medium, a second memory area that stores data and second...
7110322 Memory module including an integrated circuit device  
A memory module including an integrated circuit is disclosed. In one particular exemplary embodiment, the memory module may comprise a plurality of memory devices and an integrated circuit device...
7110321 Multi-bank integrated circuit memory devices having high-speed memory access timing  
Integrated circuit memory devices support write and read burst modes of operation with uniformly short interconnect paths that provide high-speed memory access timing characteristics. These memory...
7110320 Nonvolatile semiconductor memory  
Disclosed is a nonvolatile memory system including at least one nonvolatile memory each having a plurality of nonvolatile memory cells and a buffer memory; and a control device coupled to the...
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