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7391649 Page buffer and non-volatile memory device including the same  
In one aspect, a non-volatile memory device includes a non-volatile memory cell array and a page buffer. The page buffer includes a sense node selectively connected to a bit line of the memory cell...
7391645 Non-volatile memory and method with compensation for source line bias errors  
Source line bias is an error introduced by a non-zero resistance in the ground loop of the read/write circuits. During sensing the source of a memory cell is erroneously biased by a voltage drop...
7388791 Signal interface  
Plural transmitter units generate plural currents corresponding to plural logical values, respectively, and propagate the currents to a common signal line. The common signal line synthesizes the...
7388770 One-time programable memory with additional programming time to ensure hard breakdown of the gate insulating film  
A nonvolatile semiconductor memory device includes a storage element which is programmed with information by breaking an insulating film by application of electrical stress to the storage element,...
7385852 Circuit for generating step-up voltage in non-volatile memory device  
A circuit for generating a step-up voltage, in which it can reduce ripples. The circuit includes a high voltage transfer switch, a high voltage switching unit that pumps a high voltage in response...
7379362 Semiconductor memory device having a hierarchical bit line structure  
In semiconductor memory devices having hierarchical bit line structures, a transfer transistor provided between a main bit line and a sub-bit line hinders achievement of a high speed and a low...
7379354 Methods and apparatus to provide voltage control for SRAM write assist circuits  
Methods and apparatus to control voltage output of a write assist circuit are disclosed. An example method includes regulating pull down voltage from a write assist circuit having a write assist...
7379353 Voltage Pumping Device  
A voltage pumping device is disclosed. The device comprises a reference voltage generator for generating a reference voltage having different levels depending on whether a semiconductor device is...
7379338 Method and system for regulating a program voltage value during multilevel memory device programming  
Regulating a program voltage value during multilevel memory device programming includes utilizing a program path duplicate in an output pump regulator circuit. Further, the output pump regulator...
7376042 Boosted clock circuit for semiconductor memory  
A memory component includes at least one memory bank array, a DQ region, a clock tree, and a voltage generator. The memory component is configured in a semiconductor wafer. The at least one memory...
7376032 Method and apparatus for a dummy SRAM cell  
A dummy SRAM cell for use in a dummy bit line circuit uses the same transistors as used in a standard SRAM cell, which includes first and second subsets of transistors configured as first and...
7376023 Semiconductor memory device with MOS transistors each having floating gate and control gate and method of controlling the same  
A semiconductor memory device includes memory cells, a memory cell array, a first voltage generating circuit, a reference voltage generating circuit, and a first voltage control circuit. Each of...
7372766 Semiconductor memory device  
A semiconductor memory device may include a switching unit to selectively connect a bitline pair and a pair of input/output lines in response to a column selection line signal; a column selection...
7372748 Voltage regulator in a non-volatile memory device  
System and method for controlling voltage in a non-volatile memory system is provided. The system includes a voltage regulator that monitors an output voltage (VDD) and a mirror voltage (Vmirror)....
7372747 Flash memory device and voltage generating circuit for the same  
A flash memory device and a voltage generating circuit for the same. The flash memory includes a memory cell array configured with a plurality of memory cells, a voltage generating circuit for...
7372717 Methods for resistive memory element sensing using averaging  
A system for determining the logic state of a resistive memory cell element, for example an MRAM resistive cell element. The system includes a controlled voltage supply, an electronic charge...
7369452 Programmable cell  
A device having an OTP memory is disclosed. A program state of the OTP device is stored at a fuse that is connected in series between a first node and a latch. During a program mode, the first node...
7369446 Method and apparatus to prevent high voltage supply degradation for high-voltage latches of a non-volatile memory  
An improved cross-coupled CMOS high-voltage latch that is used for storing data bits to be written to memory cells of a non-volatile memory is provided with a switching circuit that, during writing...
7369441 Sensing circuit for multi-level flash memory  
A sensing circuit for multi-level flash memory is disclosed. The advantages of the sensing circuit are reducing the circuit size, reducing the testing time for tuning reference voltage and...
7369438 Combo memory design and technology for multiple-function java card, sim-card, bio-passport and bio-id card applications  
A combination volatile and nonvolatile memory integrated circuit has at least one volatile memory array placed on the substrate and multiple nonvolatile memory arrays. The volatile and nonvolatile...
7366048 Bulk bias voltage level detector in semiconductor memory device  
There is provided a bulk bias voltage VBB level detector in a semiconductor memory device capable of improving tWR fail generated at a low temperature by compensating a temperature variance. The...
7366046 DRAM density enhancements  
In one embodiment, a sense amplifier includes: a differential amplifier adapted to amplify a voltage difference between a pair of bit lines; and a self-bias generation circuit adapted to reduce an...
7366040 Method of reducing settling time in flash memories and improved flash memory  
A method of biasing word lines in a flash memory array wherein a selected word line is selected for a reading operation during data access includes the steps of biasing deselected word lines with a...
7366037 Semiconductor memory  
A semiconductor memory includes: first and second bit lines; a precharge circuit for precharging the first and second bit lines to a predetermined potential; a plurality of memory cells each...
7366036 Memory device with control circuit for regulating power supply voltage  
A Local Dynamic Power Controller (LDPC) generates and deliver to a load a full swing voltage supply signal and a reduced swing voltage supply signal. Both the full and reduce voltage supply signals...
7366035 Ferroelectric memory and method of driving the same  
A ferroelectric memory includes: a memory cell array in which a plurality of memory cells are disposed, a plurality of wordlines, a plurality of platelines, and a plurality of wordline driver...
7366019 Nonvolatile memory  
There is provided a non-volatile memory capable of being supplied with two varieties of externally supplied voltages, stabilizing the operation thereof, at a voltage in the vicinity of a threshold...
7362646 Semiconductor memory device  
A semiconductor memory device includes a memory cell array provided in a cell array area and including a plurality of memory cells, a source potential line which applies a source potential to the...
7362622 System for determining a reference level and evaluating a signal on the basis of the reference level  
A circuit exhibits a signal input, means for determining a reference level on the basis of properties of a signal received at the signal input. In addition, the circuit further exhibits means for...
7362604 Apparatus and method for programming an array of nonvolatile memory cells including switchable resistor memory elements  
A non-volatile memory cell includes a switchable resistor memory element in series with a switch device. An array of such cells may be programmed using only positive voltages. A method for...
7362167 Voltage generator  
A voltage generator reduces a stand by current in a stand by or a self-refresh mode and shortens a response time in an active mode by selectively driving a control transistor of a final driver. A...
7359271 Gate induced drain leakage current reduction by voltage regulation of master wordline  
A semiconductor integrated circuit device and method for reducing gate induced leakage current associated with circuits of the semiconductor electrical device, such as a semiconductor integrated...
7359255 Semiconductor device having auto trimming function for automatically adjusting voltage  
A reference voltage generation circuit generates a reference voltage. An internal voltage generation circuit generates an internal voltage on the basis of the reference voltage generated by the...
7359254 Controller for controlling a source current to a memory cell, processing system and methods for use therewith  
A controller for controlling a source current of a memory cell for use in a static random access memory (SRAM) includes a bias generator for supplying a bias current to the memory cell. A read...
7355904 Method and apparatus for drain pump operation  
A method and apparatus are provided for improved noise reduction from switching on and off drain pumps ( 202 ) in a high voltage generator. The drain pumps ( 202 ) are divided into groups ( 204 )...
7352643 Regulating voltages for refresh operation using flash trim bits in semiconductor memory devices  
A method and apparatus for regulating voltages in semiconductor devices. Trim bits are stored in a trim flash array, where the trim bits define a voltage value and where the voltage value is...
7352636 Circuit and method for generating boosted voltage in semiconductor memory device  
In a boosted voltage generating circuit of a semiconductor memory device, an active kicker drive signal generating circuit generates an active kicker drive signal having a first pulse duration in...
7352609 Voltage controlled static random access memory  
A static random access memory (SRAM) ( 200, 400 ) comprising a plurality of SRAM cells ( 204 ), a plurality of wordlines (WL 0 -WLN) and a voltage regulator ( 240, 240′, 300, 516 ) for driving...
7345932 Low power dissipation voltage generator  
A voltage generator circuit is described for providing a regulated voltage, such as a negative word line voltage in a semiconductor memory. The generator uses a source transistor to couple a...
7345931 Maintaining internal voltages of an integrated circuit in response to a clocked standby mode  
A method and circuit for controlling an output reference voltage generated by a reference voltage generator disposed on a memory device are provided. A signal for enabling a clocked standby mode of...
7345919 Semiconductor device that enables simultaneous read and write/read operation  
A semiconductor device includes a memory cell array including a plurality of cores, each of said cores including one block or a plurality of blocks. The semiconductor device further includes a...
7345916 Method and apparatus for high voltage operation for a high performance semiconductor memory device  
A method and apparatus are provided for high performance, high voltage memory operations on selected memory cells ( 200 ) of a semiconductor memory device ( 100 ). A high voltage generator ( 106 )...
7342819 Methods for generating a reference voltage and for reading a memory cell and circuit configurations implementing the methods  
A method and a circuit configuration for generating a reference voltage in a resistive semiconductor memory includes generating a reference voltage by connecting together two bitlines having...
RE40132 Large scale integrated circuit with sense amplifier circuits for low voltage operation  
Disclosed is a one-chip ULSI which can carry out the fixed operation in a wide range of power supply voltage (1 V to 5.5 V). This one-chip ULSI is composed of a voltage converter circuit(s) which...
7336545 Semiconductor device having switch circuit to supply voltage  
A memory cell array has memory cells arranged in a matrix form. The memory cell includes a floating gate and a control gate. Word lines are each coupled to the control gates of the memory cells...
7333385 Semiconductor memory device having the operating voltage of the memory cell controlled  
An SRAM circuit operates at a reduced operation margin, especially at a low operating voltage by increasing or optimizing the operation margin of the SRAM circuit. The threshold voltage of the...
7333373 Charge pump for use in a semiconductor memory  
In an embodiment, an improved charge pump circuit is provided to control a threshold voltage increase of a charge transmission transistor during a charge transfer period, and to prevent a latch-up...
7333370 Method to prevent bit line capacitive coupling  
Structures, systems and methods for memory cells utilizing trench bit lines formed within a buried layer are provided. A memory cell is formed in a triple well structure that includes a substrate,...
RE40075 Method of multi-level storage in DRAM and apparatus thereof  
A method of processing data having one of four voltage levels stored in a DRAM cell is comprised of sensing whether or not the data voltage is above or below a voltage level midway between a...
7327626 Self refresh control device  
Disclosed herein is a self refresh control device for reducing a current leakage of transistors in off-state. The apparatus for controlling a voltage used in a semiconductor memory device includes...
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